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* ppc4xx: PPC405GPr fix missing register definitionsNiklaus Giger2008-02-16-0/+8
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: 405EX: Correctly enable USB pinsStefan Roese2007-12-08-0/+13
| | | | | | | | This patch selects the USB data pins in the 405EX GPIO and MFC (multi function control) registers. This is done for the AMCC Kilauea and Makalu eval boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-0/+2
| | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-0/+6
| | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xxStefan Roese2007-10-31-58/+0
| | | | | | | | | | This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix small merge problems with CPCI440 and Acadia boardsStefan Roese2007-10-31-256/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-31/+644
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/zeusStefan Roese2007-08-14-0/+14
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| * ppc4xx: Add initial Zeus (PPC405EP) board supportStefan Roese2007-08-14-0/+14
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix problem in PLL clock calculationStefan Roese2007-08-13-0/+2
|/ | | | | | | This patch was originall provided by David Mitchell <dmitchell@amcc.com> and fixes a bug in the PLL clock calculation. Signed-off-by: Stefan Roese <sr@denx.de>
* Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-7/+7
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* ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-0/+9
| | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-0/+8
| | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Use do { ... } while (0) for CPR & SDR access macrosStefan Roese2007-05-22-4/+4
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add output for bootrom location to 405EZ portsStefan Roese2007-04-18-0/+2
| | | | | | | | | | | | | | Now 405EZ ports also show upon bootup from which boot device they are configured to boot: U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) Bootstrap Option E - Boot ROM Location EBC (32 bits) 16 kB I-Cache 16 kB D-Cache Board: Acadia - AMCC PPC405EZ Evaluation Board Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add AMCC PPC405EZ supportStefan Roese2007-03-21-0/+540
| | | | | | | | | | This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-0/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Added support for the SOLIDCARD III board from EurodesignHeiko Schocher2007-01-11-0/+1
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* Code cleanup.wdenk2004-12-16-4/+4
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* new 405ep defines addedstroese2004-12-16-0/+9
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* Add support for the second Ethernet interface for the 'PPChameleon' board.wdenk2004-06-06-2/+6
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* Updated for PPC405EP boards.stroese2003-12-09-0/+8
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* * Code cleanup:wdenk2003-06-27-24/+23
| | | | | | | | | - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
* PPC405EP support added.stroese2003-05-23-1/+275
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* Added edge conditioning register (ecr) for PPC405GPr.stroese2003-03-20-0/+1
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* Initial revisionwdenk2002-11-03-0/+400
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