summaryrefslogtreecommitdiff
path: root/include/pci.h
Commit message (Collapse)AuthorAgeLines
* x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson2012-12-06-0/+123
| | | | | | | | | Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: declare pciauto functions in headerLinus Walleij2012-03-30-1/+5
| | | | | | | | | | | The FSL PCI driver uses local prototypes for pciauto_[pre|post]scan_setup_bridge(), this does not seem right, so move them to the <pci.h> file. Fixed a small extern declaration too, this is harmless but distracts the view since all other prototypes are explicitly external. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pci: move pciauto_config_init() to pci.hLinus Walleij2012-03-04-0/+1
| | | | | | | | | | | | | Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCsPrabhakar Kushwaha2011-03-29-0/+1
| | | | | | | | | | The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: fix pcie configuration space read/writeLeo Liu2011-02-05-0/+2
| | | | | | | | | | | | This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Leo Liu <liucai.lfn@gmail.com> fix codingstyle and compiler warning: 'pcie_priv' defined but not used Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixupKumar Gala2011-01-14-0/+1
| | | | | | | | | | | | | | Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOWPeter Tyser2010-11-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation. - Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ... - Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus. - Changes the general formatting of the PCI device output. Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIeKumar Gala2009-08-28-0/+1
| | | | | | | | Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PCI: Add pci_last_busno() helperAnton Vorontsov2009-02-23-0/+2
| | | | | | | | | | This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* drivers/pci: Create pci_map_bar functionBecky Bruce2009-02-10-4/+24
| | | | | | | | It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala2009-02-07-1/+1
| | | | | | | | | | The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: Add support for MPC83xx PCI-E controllersAnton Vorontsov2009-01-21-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* pci: Allow for PCI addresses to be 64-bitKumar Gala2008-10-24-16/+24
| | | | | | | | | | PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* Update pci code to use phys_addr_tBecky Bruce2008-05-10-5/+5
| | | | | | | | Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts.Ed Swarthout2007-08-06-0/+6
| | | | | | | | | | | | | | | | | | All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* * Fix a bunch of compiler warnings for gcc 4.0Jon Loeliger2006-10-19-0/+3
| | | | Signed-off-by: Matthew McClintock <msm@freescale.com>
* * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on ā†µMatthew McClintock2006-08-09-0/+9
| | | | | | 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#pciWolfgang Denk2006-03-12-1/+3
|\
| * Added support for PCI prefetchable region and BARsKumar Gala2006-01-11-1/+3
| | | | | | | | | | | | | | | | | | | | | | If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
* | Fix bad declaration on pci_cfgfunc_nothingWolfgang Denk2006-03-12-2/+2
|/ | | | Patch by Sam Song, 19 Jun 2005
* Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone.Stefan Roese2005-08-01-0/+15
| | | | Patch by Steven Blakeslee, 27 Jul 2005
* * Patch by Marc Singer, 29 May 2003:wdenk2003-05-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engström, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board
* * Patch by Thomas Frieden, 13 Nov 2002:wdenk2002-11-19-1/+2
| | | | | | | | | | | | | Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined.
* Initial revisionwdenk2002-11-03-0/+475
generated by cgit v1.1 at 2024-11-09 14:19:06 +0000