| Commit message (Collapse) | Author | Age | Lines |
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Recommended frequency is 66MHz
Change divider from 4 to 3.
Signed-off-by: John Rigby <jrigby@freescale.com>
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Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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Signed-off-by: John Rigby <jrigby@freescale.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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The following MPC5121e subsystems are supported:
- low-level CPU init
- NOR Boot Flash (common CFI driver)
- DDR SDRAM
- FEC
- I2C
- Watchdog
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
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