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path: root/include/linux/usb/xhci-fsl.h
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* armv8/ls1043ardb: add USB supportGong Qianyu2015-11-30-1/+8
| | | | | | | Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-1/+1
| | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-3/+3
| | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
* include: usb: Map USB controller base addresses for LS2085ANikhil Badola2015-07-22-0/+3
| | | | | | Map USB XHCI controller base addresses for LS2085A SOC Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* include: usb: Move USB controller base address mappingNikhil Badola2015-07-22-0/+7
| | | | | | | | | Move USB controller Base address mapping from ls102xa immap to fsl xhci header. This is required to remove any warnings when controller base addresses are mapped for multiple platforms in their respective files. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* usb: fsl: Add XHCI driver supportRamneek Mehresh2015-07-22-0/+54
Add xhci driver support for all FSL socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>