| Commit message (Collapse) | Author | Age | Lines | |
|---|---|---|---|---|
| * | Handle Asynchronous DDR clock on 85xx | Kumar Gala | 2007-12-11 | -0/+1 |
| | | | | | | | | | | | The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> | |||
| * | Patch by Jon Loeliger, 16 Jul 2004: | wdenk | 2004-08-01 | -0/+15 |
| | | | | | | | | | | | | | | - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads | |||
| * | * Patches by Xianghua Xiao, 15 Oct 2003: | wdenk | 2003-10-15 | -0/+100 |
| - Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup | ||||
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