summaryrefslogtreecommitdiff
path: root/include/dt-bindings
Commit message (Collapse)AuthorAgeLines
* am437x: Add am437x_gp_evm_defconfig using CONFIG_DMMugunthan V N2015-10-22-0/+47
| | | | | | | | | | Import various DT files for am4372, an43xx pinctrl and am437x-gp-evm from Linux Kernel v4.2 Add config file for this board, enable DM, DM_GPIO, DM_SERIAL and DM_MMC. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* rockchip: Bring in RK3288 device tree file includes and bindingsSimon Glass2015-09-02-0/+418
| | | | | | | | Bring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream. Signed-off-by: Simon Glass <sjg@chromium.org>
* dra7xx: Add dra72_evm_defconfig using CONFIG_DMTom Rini2015-08-12-0/+51
| | | | | | | | | | - Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel v4.1 - Add config file for this board, enable DM and DM_GPIO Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+342
| | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
* ti: Add SPDX license identifier to omap.hSimon Glass2015-07-08-0/+2
| | | | | | | | | | | This also came from Linux - according to this thread it has a GPL v2 license like arch/arm/mach-omap2/mux.h: http://lists.denx.de/pipermail/u-boot/2015-June/217827.html Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-0/+31
| | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-0/+31
| | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* sandbox: dts: add sandbox_pmic.dtsi and include it to sandbox.dts and test.dtsPrzemyslaw Marczak2015-05-14-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds dtsi file for Sandbox PMIC. It fully describes the PMIC by: - i2c emul node - with a default settings of 16 registers - 2x buck regulator nodes - 2x ldo regulator nodes The default register settings are set with preprocessor macros: - VAL2REG(min[uV/uA], step[uV/uA], val[uV/uA]) - VAL2OMREG(mode id) Both defined in file: - include/dt-bindings/pmic/sandbox_pmic.h The Voltage ranges of each regulator can be found in: - include/power/sandbox_pmic.h The new file is included into: - sandbox.dts - test.dts Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on sandbox: Tested-by: Simon Glass <sjg@chromium.org>
* sunxi: dts: Sync all dts files with upstream kernelHans de Goede2015-05-04-0/+135
| | | | | | | | | | | Bring all the sunxi dts files (and update existing ones) from mripard/sunxi/dt-for-4.1 (which will be merged into upstream master any day now). This is necessary so that we can move all sunxi boards over to the driver model. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* dt-bindings: Add Intel Quark MRC bindingsBin Meng2015-02-06-0/+83
| | | | | | | Add standard dt-bindings macros to be used by Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: tegra: Add Tegra30 PCIe device tree nodeThierry Reding2014-12-18-1/+1
| | | | | | | | Add the device tree node for the PCIe controller found on Tegra30 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Add Tegra20 PCIe device tree nodeThierry Reding2014-12-18-1/+1
| | | | | | | | | Add the device tree node for the PCIe controller found on Tegra20 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Implement XUSB pad controllerThierry Reding2014-12-18-0/+7
| | | | | | | | | | | | | | | This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-8/+1
|\
| * arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiersStefan Roese2014-12-06-8/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | tegra: dts: Sync tegra124.dtsi with linux kernelSimon Glass2014-12-11-0/+45
|/ | | | | | | | | | Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings for pinctrl. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-11-11-0/+90
|\
| * arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates targetStefan Roese2014-11-07-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org>
* | dm: sunxi: dts: Add sun7i device tree filesSimon Glass2014-11-05-0/+525
|/ | | | | | | | | | | These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small portion of these, but we may as well have something to look forward to. The total compiled size is about 25KB. Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* dm: dts: Move omap device tree includes to correct placeSimon Glass2014-10-23-0/+97
| | | | | | | These ended up in arch/arm/dts/dt-bindings temporarily, but in fact the correct place is now include/dt-bindings. Move them to be consistent. Signed-off-by: Simon Glass <sjg@chromium.org>
* tegra: dts: Add serial port detailsSimon Glass2014-09-10-0/+1115
| | | | | | | | | | | | | | | | Some Tegra device tree files do not include information about the serial ports. Add this and also add information about the input clock speed. The console alias needs to be set up to indicate which port is used for the console. Also add a binding file since this is missing. Series-changes; 5 - Add full serial port nodes from Linux tree (commit fc9d4dbe) - Use /chosen/stdout-path instead of /aliases/console to specify the console Signed-off-by: Simon Glass <sjg@chromium.org>
* tegra: dts: Bring in GPIO bindings from linuxSimon Glass2014-06-20-0/+107
These files are taken from Linux 3.14. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.1 at 2024-11-05 09:13:57 +0000