arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	powerpc/mpc8xxx: Add fine timing support for DDR3	York Sun	2012-08-23	-1/+6
\| \| \| \| \| \| \| \|	When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification	Ira W. Snyder	2011-11-29	-0/+7
\| \| \| \| \| \| \| \| \| \|	Newer JEDEC DDR3 SPD Specifications define several additional values for the DDR3 module_type field which were undefined when this code was written. Update the code to handle the newer module types. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	Adding more SPD registers	York Sun	2011-07-11	-1/+3
\| \| \| \| \| \| \|	Adding byte 32 and 33 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements	Kyle Moffett	2011-04-04	-9/+19
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/8xxx: Enable DDR3 RDIMM support	york	2010-07-26	-0/+14
\| \| \| \| \| \| \| \| \|	Enabled registered DIMMs using data from SPD. RDIMMs have registers which need to be configured before using. The register configuration words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software should read those RCWs and put into DDR controller before initialization. Signed-off-by: York Sun <yorksun@freescale.com>
*	fsl-ddr: add the DDR3 SPD infrastructure	Dave Liu	2009-03-30	-1/+12
\| \| \| \| \| \| \| \| \|	- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
*	Add proper SPD definitions for DDR1/2/3	James Yang	2008-08-27	-0/+292
	Also adds helper functions for DDR1/2 to verify the checksum. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>