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* powerpc: remove not used CONFIG_SYS_TFTP_LOADADDRtrem2012-12-15-9/+0
| | | | | | | CONFIG_SYS_TFTP_LOADADDR is defined on severals boards, but it's never used. So we can safely removed it. Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* omap3_evm: Let CONFIG_EFI_PARTITION be set for SPLTom Rini2012-12-13-3/+0
| | | | | | | | | The #ifdef here is not enough to stop part_efi.c from being built, only being unused. And with recent changes this now leads to warnings. The easiest solution here is to just let the garbage collection at link time do its job. Signed-off-by: Tom Rini <trini@ti.com>
* gpt: Enable support for GPT partition table restoration at Samsung's TratsLukasz Majewski2012-12-13-1/+27
| | | | | | | | | Enable support for GPT partition table restoration at Samsung's Trats development board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
* exynos: Enable hashing functions and EDID for smdk5250Simon Glass2012-12-11-0/+7
| | | | | | | Enable SHA1/SHA256 hashing and the hash command. Also enable EDID support for reading from an LCD. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2012-12-07-17/+31
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| * x86: Fix coreboot config to boot on ChromebookSimon Glass2012-12-06-14/+12
| | | | | | | | | | | | | | | | | | | | The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Turn on support for EFI's GPT in the coreboot configGabe Black2012-12-06-0/+3
| | | | | | | | | | | | | | This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: coreboot: Enable video displaySimon Glass2012-12-06-2/+8
| | | | | | | | | | | | Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-06-1/+1
| | | | | | | | | | | | | | | | | | This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable CONFIG_CMD_ZBOOT for corebootSimon Glass2012-12-06-0/+3
| | | | | | | | | | | | Enable this option to support booting a zImage. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable ICH6 GPIO controller for corebootSimon Glass2012-12-06-0/+4
| | | | | | | | | | | | Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Change e-mail address of Luka PerkovLuka Perkov2012-12-07-2/+2
|/ | | | | | | Change e-mail address of Luka Perkov. Signed-off-by: Luka Perkov <luka@openwrt.org> CC: Luka Perkov <uboot@lukaperkov.net>
* 4xx: Fix PCI memory mapping on CPCI405 boardsMatthias Fuchs2012-12-06-4/+4
| | | | | | | | This patch fixes an issue with overlapping PCI regions on boards with more than 64MB RAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* mpc5200: Add a3m071 board supportStefan Roese2012-12-05-0/+380
| | | | | | | This patch adds support for the a3m071 board based on the MPC5200. Signed-off-by: Stefan Roese <sr@denx.de>
* x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass2012-11-30-0/+1
| | | | | | This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Select stdio devices for corebootSimon Glass2012-11-30-0/+12
| | | | | | | We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-x86Tom Rini2012-11-28-10/+7
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| * x86: coreboot: Enable LPC TPMSimon Glass2012-11-28-0/+4
| | | | | | | | | | | | Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Remove coreboot start16 codeSimon Glass2012-11-28-1/+1
| | | | | | | | | | | | | | Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Put global data on the stackGraeme Russ2012-11-28-9/+2
| | | | | | | | | | | | | | | | | | | | Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2012-11-28-8/+60
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| * powerpc/corenet_ds: move SATA config to board configurationZang Roy-R619112012-11-27-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/P2041RDB: Fix Flash address LAW addressYork Sun2012-11-27-4/+10
| | | | | | | | | | | | | | | | | | P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet connector. It is necessary to use the same base address for correct LAW address. An offset is added for NOR flash. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add support for the Freescale P5040DS Superhydra reference boardTimur Tabi2012-11-27-0/+40
| | | | | | | | | | | | | | | | | | The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/qoriq: Move FMAN microcode locationYork Sun2012-11-27-3/+3
| | | | | | | | | | | | | | | | | | Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning of this virtual bank so that this bank can store RCW or be used together with other banks to store large images. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mmc: tegra: use bounce buffer APIsStephen Warren2012-11-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In some cases (e.g. user load commands) this cannot be guaranteed by callers of the MMC APIs. To solve this, modify the Tegra MMC driver to use the new bounce_buffer_*() APIs. Note: Ideally, all U-Boot code will always provide address- and size- aligned buffers, so a bounce buffer will only ever be needed for user- supplied buffers (e.g. load commands). Ensuring this removes the need for performance-sucking bounce buffer cache management and memcpy()s. The one known exception at present is the SCR buffer in sd_change_freq(), which is only 8 bytes long. Solving this requires enhancing struct mmc_data to know the difference between buffer size and transferred data size, or forcing all callers of mmc_send_cmd() to have allocated buffers using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not enforced in any way at present, and so cannot be assumed by the core MMC code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Replace CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER in configsStephen Warren2012-11-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed converting a few boards over to the new option. Fix this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mmc: at91sam9x5: support to save environment in mmcWu, Josh2012-11-27-3/+16
|/ | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2012-11-26-71/+108
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| * powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL bootScott Wood2012-11-26-36/+33
| | | | | | | | | | | | | | | | | | | | | | | | This allows DDR configuration to be deferred to the final U-Boot image, which is able to make use of SPD data. The SPL itself cannot use SPD due to code size constraints. It previously used fixed register values for DDR configuration, and those values did not work on the p2020rdb-pca board I tested with. It's possible that different revisions of the board require different settings. Using SPD eliminates that problem. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory mapScott Wood2012-11-26-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Sort by address, and fix column alignment - Don't label things as localbus that aren't. Instead, put chipselect info at the end of the description for localbus windows. Note that NAND/NOR have their chipselects swapped when booting from NAND, and CS2 can be either PMC or VSC7385 depending on hwconfig. - Shrink NAND to the 32K that's actually mapped in the localbus - Assign an address and size to L2 SRAM. Remove the similarly named but unintelligible "L2 SDRAM(REV.)". - Remove the untrue comment about L1 stack being mapped with TLB0. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new splScott Wood2012-11-26-26/+28
| | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.Scott Wood2012-11-26-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some small SPLs do not use nand_base.c, and a subset of those also require a special driver. Some SPLs need software ECC but others can't fit it. All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these symbols added to preserve existing behavior. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: use positive logic for including bits of NAND, rather than a MINIMAL symbol that excludes things.
* | omap3_beagle: use new MUSB intstead of the old oneIlya Yanok2012-11-20-7/+4
| | | | | | | | | | | | | | | | | | | | Enable using of new MUSB framework on Beagle. NOTE! This is not just a change of backend code: top-level behavior is also changed, we now use USB device port for USB Ethernet instead of serial. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | omap3_beagle: add musb-new initIlya Yanok2012-11-20-0/+2
| | | | | | | | | | | | Add initialization for new MUSB framework. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | am3517_evm: switch to musb-newIlya Yanok2012-11-20-21/+16
| | | | | | | | | | | | Use new musb framework instead of the old one on AM3517_EVM. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | am335x_evm: enable both musb gadget and hostIlya Yanok2012-11-20-0/+27
| | | | | | | | | | | | | | Enable musb gadget in Ethernet mode on port 0 and musb host on port1. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | tegra: Enable USB keyboardAllen Martin2012-11-20-0/+6
| | | | | | | | | | | | | | | | Enable USB keyboard for seaboard and ventana Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | tegra: move TEGRA_DEVICE_SETTINGS to tegra-common-post.hAllen Martin2012-11-20-9/+19
| | | | | | | | | | | | | | | | | | | | Move environment settings for stdin/stdout/stderr to tegra-common-post.h and generate them automaticaly based on input device selection. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | boards: remove the no longer used CONFIG_EHCI_DCACHEJeroen Hofstee2012-11-20-10/+0
|/ | | | | | | | | | | | | | | | CONFIG_EHCI_DCACHE was removed by commit b8adb12 "USB: Drop cache flush bloat in EHCI-HCD". Remove the defines from the boards configs as well. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> cc: Marek Vasut <marex@denx.de> cc: Stefan Roese <sr@denx.de> cc: Tom Rini <trini@ti.com> cc: Wolfgang Denk <wd@denx.de> cc: Thierry Reding <thierry.reding@avionic-design.de> cc: Tom Warren <twarren@nvidia.com> cc: Stephen Warren <swarren@nvidia.com> cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2012-11-19-80/+116
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| * M68K: eb_cpu5282: general update and enhanced board supportJens Scharsig (BuS Elektronik)2012-11-14-36/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - update clock settings for higher perfomance - change standard baud rate to 115200 - fix flash base address - remove unused defines - add I2C support - switch form board dependent flash to cfi - remove board dependent flash code - use sdram bank 0 instead of bank 1 on boot - enable on board frame buffer instead external - remove fake mac address form config - add watchdog support - add status led support Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> [agust: fixed small style issues and build warning] Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * power:pmic: Rename CONFIG_DIALOG_PMIC defines to CONFIG_DIALOG_POWERŁukasz Majewski2012-11-14-1/+1
| | | | | | | | | | | | | | | | Rename CONFIG_DIALOG_PMIC to CONFIG_DIALOG_POWER Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
| * power:pmic: Rename CONFIG_PMIC* defines to CONFIG_POWERŁukasz Majewski2012-11-14-42/+42
| | | | | | | | | | | | | | | | Rename all CONFIG_PMIC* defines to CONFIG_POWER* Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
| * arm:trats:pmic: Enable battery support at Samsung's TRATS boardŁukasz Majewski2012-11-14-0/+2
| | | | | | | | | | | | | | | | | | Support for TRATS battery has been added. It is treated as a "normal" power related device and thereof controlled by pmic/power subsystem. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * arm:trats:pmic: Enable fuel-gauge (MAX17042) at Samsung's TRATS boardŁukasz Majewski2012-11-14-0/+2
| | | | | | | | | | | | | | | | | | FG IC built into the MAX8997 device (compliant to MAX17042) is enabled at TRATS. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * arm:trats:pmic: Enable MUIC (MAX8997) at Samsung's TRATS boardŁukasz Majewski2012-11-14-0/+2
| | | | | | | | | | | | | | | | MUIC IC built into the MAX8997 device is enabled at TRATS. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
* | nios2: remove asm/status_led.hThomas Chou2012-11-10-0/+2
| | | | | | | | | | | | | | | | | | The file has a wrong inline keyword of __led_toggle(), which causes compilation error. And its content is defined in common status_led.h. So define CONFIG_BOARD_SPECIFIC_LED in board config files and remove this header file. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* | microblaze: Flush caches before enabling themMichal Simek2012-11-07-0/+4
|/ | | | | | | | Flushing caches is necessary because of soft reset which doesn't clear caches. Signed-off-by: Michal Simek <monstr@monstr.eu> Reviewed-by: Marek Vasut <marex@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-avr32Tom Rini2012-11-05-9/+0
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