| Commit message (Collapse) | Author | Age | Lines |
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Various changes to highbank config:
Enable EFI partitions
Enable ext4 and FAT filesystems
Enable bootz command and raw initrd
Increase cmd and print buffer size to 1K
Change serial baudrate to 115200
Enable hush shell
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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Fix the license header introduced by the following patches
Add TWR-P10xx board support
Add T4240EMU target
IDT8T49N222A configuration code
Add C29x SoC support
Add support for C29XPCIE board
Signed-off-by: York Sun <yorksun@freescale.com>
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C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module. It
includes C293PCIE board, C293PCIE board and C291PCIE board.
- 512KB platform SRAM in addition to 512K L2 Cache/SRAM
- 512MB soldered DDR3 32bit memory
- CPLD System Logic
- 64MB x16 NOR flash and 4GB x8 NAND flash
- 16MB SPI flash
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Singed-off-by: Po Liu <Po.Liu@freescale.com>
[yorksun: Fixup include/configs/C29XPCIE.h]
Signed-off-by: York Sun <yorksun@freescale.com>
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1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
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1) Add support in B4860 board files for using IDT driver where
IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
that generate different refclks for SerDes modules, used this driver
for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
for CPRI to work. CPRI works on 122.88MHz and default refclks coming
on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
to b4860qds board file, as SerDes1 Refclk1 would come from
PHY MUX in case of certain protocols, that have been checked here.
This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB.
DDR changed from DDR2 1G to DDR3 2G.
NAND: 128 MiB
Flash: 64 MiB
Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
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JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.
Signed-off-by: York Sun <yorksun@freescale.com>
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Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
ECC for DDR is disabled due the procedure to load images
No board FPGA (QIXIS)
NOR flash has 32-bit port for higher loading speed
IFC and I2C timing don't really matter, so set them fast
No ethernet
Signed-off-by: York Sun <yorksun@freescale.com>
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CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef.
Signed-off-by: York Sun <yorksun@freescale.com>
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Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.
Signed-off-by: York Sun <yorksun@freescale.com>
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TWR-P1025 Specification:
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Memory subsystem:
512MB DDR3 (on board DDR)
64Mbyte 16bit NOR flash
One microSD Card slot
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC3: Connected to Atheros AR8035 GETH PHY
UART:
Two UARTs are routed to the FDTI dual USB to RS232 convertor
USB: Two USB2.0 Type A ports
I2C:
AT24C01B 1K Board EEPROM (8 bit address)
QUICC Engine:
Connected to DP83849i PHY supply two 10/100M ethernet ports
QE UART for RS485 or RS232
PCIE:
One mini-PCIE slot
Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
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This patch changes some features of the a3m071/a4m2k board support:
- Add bootcounter support
- Update MTD env default to correct values
- Add mtdparts to bootargs for mtd partitioning via kernel cmdline
- Added some default env variables for easy updating (kernel, dtb)
- Change README to the updated flash locations
Signed-off-by: Stefan Roese <sr@denx.de>
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Tested spi on zynq board with sst flash by enabling
CONFIG_ZYNQ_SPI.
sf probe 1:1 0 0
SF: Detected SST25WF080 with page size 4 KiB, total 1 MiB
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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In case only the CONFIG_SYS_I2C_SPEED is set in configuration file,
the CONFIG_SYS_I2C_SOFT_SPEED is defined as CONFIG_SYS_I2C_SPEED.
The CONFIG_SYS_I2C_SOFT_SPEED is then used throughout the driver.
Unfortunatelly, due to a typo in the driver, instead of defining
CONFIG_SYS_I2C_SOFT_SPEED, an CONFIG_SYS_SOFT_I2C_SPEED was defined
and therefore the driver failed to compile. The same applies for
CONFIG_SYS_I2C_SOFT_SLAVE , where the swap happens as well.
This patch fixes the issue.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
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Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
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Aside from microblaze, all other SoCs/boards/vendors store their DT files
in board/$vendor/dts/$soc-$board.dts. Move microblaze-generic.dts to this
location for consistency.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <monstr@monstr.eu>
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CONFIG_SYS_FLASH_PROTECTION was active on most gdsys boards by default,
while hardware flash protection was not implemented.
Hardware support was added recently and we get into trouble because backward
compatibility is broken (u-boot can't unprotect the protected flash after a
downgrade). So we decided to disable hardware flash protection for all our boards.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
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A set of accessor functions was added to be able to access not only
memory mapped FPGA in a generic way.
Thanks to Wolfgang Denk for getting this sorted properly.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
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Add a header file, setup.h, which copy from Linux source code,
this file contain structures are used to pass initialisation parameters
to Linux. Enable this function on adp-ag101/adp-ag101p target
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
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Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
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The original adp-ag101/adp-ag101p initialize only one bank(64MB)
by default at boot time, but it is not enough for some application,
so increasing to two banks(128M).
Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
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Signed-off-by: Tom Rini <trini@ti.com>
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Conflict over SPDX changes means that one change was effectively dropped
as it was fixing typos in a removed hunk of text.
Conflicts:
arch/mips/cpu/mips64/start.S
Signed-off-by: Tom Rini <trini@ti.com>
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Qemu emulates a PCNET PCI card for the Malta CoreLV board.
Enable the pcnet driver and add board specific ethernet
initialization function to bring it up. Also enable the
CONFIG_CMD_NET and CONFIG_CMD_PING options.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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Qemu emulates the Galileo GT64120 System Controller
which provides a CPU bus to PCI bus bridge.
The patch adds driver for this bridge and enables
PCI support for the emulated Malta board.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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Add minimal support for the MIPS Malta CoreLV board
emulated by Qemu. The only supported peripherial is
the UART.
This is enough to boot U-Boot to the command prompt
both in little and big endian mode.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
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The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.
Conflicts:
board/sandburst/common/ppc440gx_i2c.c
board/sandburst/common/ppc440gx_i2c.h
Signed-off-by: Tom Rini <trini@ti.com>
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This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.
Signed-off-by: Alison Wang <b18965@freescale.com>
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Due to the new I2C framework we need to adapt the u-boot update
function. Due to the new framework all i2c leafs behind a mux are
present in the system and not only those who are defined and used. So it
is bus number 5 after the rework.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Heiko Schocher <hs@denx.de>
cc: Prafulla Wadaskar <prafulla@marvell.com>
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Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
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This enables CONFIG_SYS_I2C on Tegra, updating existing boards and the Tegra
i2c driver to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heiko Schocher <hs@denx.de>
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as the keymile boards use now the new i2c multibus/multiadapter
framework, remove the EEprom_ivm Environmentvar, as not longer
needed.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-By: Holger Brunck <holger.brunck@keymile.com>
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- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
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- added to soft_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
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Missing space for loaddtb command has been added. When missing, ext4load
fails with wrong number of passed parameters.
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
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The gdsys ControlCenter Digital board is based on a Freescale P1022 QorIQ SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On board peripherals include:
- 2x GbE
- Lattice ECP3 FPGA connected via PCIe
- mSATA RAID1
- USB host
- DisplayPort video output
- Atmel TPM
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The files board/qi/qi_lb60/qi_lb60.c and include/configs/qi_lb60.h were
licensed under the GPL v3 or later, and not v2 or later. As this is
incompatible with the project, revert this board support until the
responsible parties are available to re-license (if so desired) under
GPL v2.
Signed-off-by: Tom Rini <trini@ti.com>
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Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.
Conflicts:
arch/arm/dts/exynos5250.dtsi
Signed-off-by: Tom Rini <trini@ti.com>
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OpenEmbedded has change partitioning layout of generated image so it
does not raise warnings during the boot regarding unkown partition
being used for U-Boot.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
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OpenEmbedded has change partitioning layout of generated image so it
does not raise warnings during the boot regarding unkown partition
being used for U-Boot.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
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OpenEmbedded has change partitioning layout of generated image so it
does not raise warnings during the boot regarding unkown partition
being used for U-Boot.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
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OpenEmbedded has change partitioning layout of generated image so it
does not raise warnings during the boot regarding unkown partition
being used for U-Boot.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
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