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* spl, common, serial: build SPL without serial supportHeiko Schocher2015-08-12-0/+4
| | | | | | | | | This patch enables building SPL without CONFIG_SPL_SERIAL_SUPPORT support. Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Ensure we build arch/arm/imx-common on mx28] Signed-off-by: Tom Rini <trini@konsulko.com>
* port vexpress to use distro boot commandsDennis Gilmore2015-08-12-17/+17
| | | | | | | | remove options defined in the distro defaults add distro bot commands set scriptaddr value Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* Move setting CONFIG_BOOTP_VCI_STRING to before including the vexpress-common ↵Dennis Gilmore2015-08-12-3/+3
| | | | | | header Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* ARM: highbank: remove DRAM bank setupRob Herring2015-08-12-1/+2
| | | | | | | | | | | On the highbank platform the SoC's management controller firmware will probe the DRAM modules and populates the initial device tree with the correct values. Therefore the memory sizes in the DT are already correct, so remove U-Boot's DRAM bank setup so the memory node is not "fixed up" by u-boot. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-08-0/+12
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| * sunxi: Do not add a stdout-path alias to dts on boards without a serial portHans de Goede2015-08-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not add a bogus (pointing to a non existing serial port) stdout-path alias to dts on boards without a serial port. Note that we still define CONS_INDEX as this is used by the SPL where we do not use DM_SERIAL and thus CONFIG_REQUIRE_SERIAL_CONSOLE is not honored. We are getting away with this because the sun5i die actually has an uart0, which in the A13 package is not routed to the outside, so we are simply sending SPL bootup messages to the tx pin at the edge of the die, and they go no further from there... And sofar we only have one A13 board which does not have a serial port, all others do have a serial port. This kinda makes sense since the A13 is a much lower pincount package compared to all the other sunxi SoCs. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: nand: Add board configuration optionsPiotr Zierhoffer2015-08-08-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND. This commit also introduces the configurable options in Kconfig. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD usefulMarek Vasut2015-08-08-0/+4
| | | | | | | | | | | | | | | | Enable the mtdparts command and related options to make support for SPI NOR MTD useful in any way. With the mtdparts command in place, it is possible to use partition of the SPI NOR in U-Boot. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Fix LOADADDRMarek Vasut2015-08-08-2/+2
| | | | | | | | | | | | | | | | | | Setting LOADADDR to 0x8000 is a bad idea, it is very likely that some kind of overlap will happen. Move the LOADADDR 0x01000000 (16MiB from start of RAM) to make sure no overlap happens when loading kernel for example. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Enable CONFIG_SPI_FLASH_BARMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | | | | This is needed to access broken (read: Micron) SPI flashes which are larger than 16 MiB and don't correctly support 4-byte addressing. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL buildMarek Vasut2015-08-08-0/+2
| | | | | | | | | | | | | | We do not need full MTD support in the SPL build, it only adds size and is not usable in any way. Exclude it. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Zap incorrect config optionsMarek Vasut2015-08-08-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to disable support for partitions in the SPL, we can support partitions in SPL perfectly well. This is likely some remnant from old times, so just remove this configuration option. Moreover, the CRC32 chunk size doesn't have to be adjusted anymore, since both the GD and malloc area are in RAM by the time this CRC check can be used and there's plenty of space. Zap this abomination as well. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Move SPL GD and malloc to RAMMarek Vasut2015-08-08-6/+8
| | | | | | | | | | | | | | | | | | | | | | Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: misc: Reset ethernet from OFMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Probe ethernet GMAC from OFMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Export bootmode into environment variableMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | | | | | | setenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from QSPIMarek Vasut2015-08-08-0/+9
| | | | | | | | | | | | | | Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from SD/MMCMarek Vasut2015-08-08-0/+14
| | | | | | | | | | | | | | | | | | | | Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Remove custom linker scriptMarek Vasut2015-08-08-3/+0
| | | | | | | | | | | | | | | | Remove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Merge spl_board_init() into board_init_f()Marek Vasut2015-08-08-1/+0
| | | | | | | | | | | | | | | | | | | | The code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: enable the Altera SDRAM controller driverDinh Nguyen2015-08-08-0/+5
| | | | | | | | | | | | | | Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: Move generated files into qts subdirMarek Vasut2015-08-08-6/+6
|/ | | | | | | | | Move all the files generated by Quartus into the qts/ subdir of the board/altera/socfpga dir to make them explicitly separate from the generic U-Boot code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-112/+66
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| * exynos: Add support for springSimon Glass2015-08-05-0/+20
| | | | | | | | | | | | | | | | | | | | Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
| * video: Remove the old parade driverSimon Glass2015-08-05-4/+0
| | | | | | | | | | | | | | We have a new one which uses driver model and device tree configuration. Remove the old one. Signed-off-by: Simon Glass <sjg@chromium.org>
| * power: Remove old TPS65090 driversSimon Glass2015-08-05-2/+0
| | | | | | | | | | | | | | Remove the old drivers (both the normal one and the cros_ec one) now that we have new drivers that use driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5250-specific board codeSimon Glass2015-08-05-0/+2
| | | | | | | | | | | | | | Now that most exynos5250 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5420-specific board codeSimon Glass2015-08-05-0/+2
| | | | | | | | | | | | | | | | Now that exynos5420 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: config: Move common options to the common headers and tidy upSimon Glass2015-08-05-90/+39
| | | | | | | | | | | | | | | | | | | | Many options are duplicated on the exynos5 boards. Move these to the common files. Also some options are not used so can be removed. Tidy this up to make the files easier to maintain. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: Enable new features for exynos5 boardsSimon Glass2015-08-05-19/+6
| | | | | | | | | | | | | | Enable PMICs, regulators and the like so that new drivers will be made available. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra: Add p2371-0000 boardStephen Warren2015-08-06-0/+65
| | | | | | | | | | | | | | | | | | | | | | P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add e2220-1170 boardStephen Warren2015-08-06-0/+65
| | | | | | | | | | | | | | | | | | E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various expansion modules. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: p2571: remove another unused defineStephen Warren2015-08-06-3/+0
| | | | | | | | | | | | | | | | CONFIG_MAX77620_POWER isn't used anywhere. Don't define it in p2571.h. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: enable GPU DT node when appropriateAlexandre Courbot2015-08-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T124/210 requires some specific configuration (VPR setup) to be performed by the bootloader before the GPU can be used. For this reason, the GPU node in the device tree is disabled by default. This patch enables the node if U-boot has performed VPR configuration. Boards enabled by this patch are T124's Jetson TK1 and Venice2 and T210's P2571. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: move VPR configuration to a later stageAlexandre Courbot2015-08-06-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot is responsible for enabling the GPU DT node after all necessary configuration (VPR setup for T124) is performed. In order to be able to check whether this configuration has been performed right before booting the kernel, make it happen during board_init(). Also move VPR configuration into the more generic gpu.c file, which will also host other GPU-related functions, and let boards specify individually whether they need VPR setup or not. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: P2571: Clean up config fileTom Warren2015-08-05-6/+1
| | | | | | | | | | | | | | Removed NS16550_COM1 #define, not used since there's no SPL for T210 Also changed the number of USB controllers to 1 as only USBD is used. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: spi: Move TEGRA114_SPI switch to defconfigsTom Warren2015-08-05-10/+0
| | | | | | | | | | | | | | | | | | | | | | All T114+ Tegra boards should be using the Kconfig TEGRA114_SPI switch. Remove it from include/config and put it into defconfig. Also removed unused TEGRA114_SPI_CTRLS from T114+ configs. All Tegra SoCs build OK with this change. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | T210: P2571: Restore USB gadget mode (ums)Tom Warren2015-08-05-0/+1
|/ | | | | | | | | | The tegra-common-usb-gadget.h include was causing some build problems in ci_udc.c with a 64-bit gcc in an earlier version of the T210 patches, but it is working fine now, so restore it. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* configs: Remove CONFIG_SERIAL_MULTIStephen Warren2015-08-05-16/+0
| | | | | | | This config option isn't used anywhere at all. Remove all places that define/enable the option. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-05-25/+78
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| * x86: Add definitions for the x86-efi board and plumb it inBen Stoltz2015-08-05-0/+34
| | | | | | | | | | | | | | | | Add configuration and Kconfig changes for this board. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: minnowmax: Drop the old PCI settingsSimon Glass2015-08-05-12/+0
| | | | | | | | | | | | | | | | These are now in the device tree so we don't need to use the CONFIG options. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Drop CONFIG_DCACHE_RAM_MRC_VAR_SIZE from header fileSimon Glass2015-08-05-1/+0
| | | | | | | | | | | | | | This is provided in Kconfig so we don't need it here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Move CONFIG_X86_SERIAL to KconfigSimon Glass2015-08-05-10/+1
| | | | | | | | | | | | | | Move this config option to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Move Chrome OS options to defconfigSimon Glass2015-08-05-3/+0
| | | | | | | | | | | | | | Drop these from the header file and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: bayleybay: Configure PCI IRQBin Meng2015-08-05-0/+1
| | | | | | | | | | | | | | | | Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add Intel Bayley Bay board supportBin Meng2015-08-05-0/+45
| | | | | | | | | | | | | | | | Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-10 05:54:00 +0000