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* arm: am437x: Introduce new board cm-t43Nikita Kiryanov2015-08-12-0/+182
| | | | | | | | | | | Add initial support for CM-T43, an AM437x based SoM. This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM detection. Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board.Peter Griffin2015-08-12-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's. This initial port adds support for: - 1) Serial 2) eMMC / SD card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Notes: eMMC has been tested with basic reading of eMMC partition into DDR. I have not tested writing / erasing. Due to lack of clock control it won't be running in the most performant high speed mode. SD card slot has been tested for reading and booting kernels into DDR. It is also currently configured to save the u-boot environment to the SD card. USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage are correctly enumerated. GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs. Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFOLokesh Vutla2015-08-12-0/+1
| | | | | | | | | | Add print_cpuinfo() function and enable CONFIG_DISPLAY_CPUINFO for keystone platforms, so that cpu info can be displayed during boot. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* integrator: switch to DM serial portLinus Walleij2015-08-12-20/+5
| | | | | | | | This switches the Integrator boards over to using the device model for its serial ports. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ti: drop value from CONFIG_SYS_NAND_BUSWIDTH_16BITStefano Babic2015-08-12-12/+12
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mcx: add Ethernet over USBStefano Babic2015-08-12-0/+3
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: fix NAND support for mcx boardStefano Babic2015-08-12-0/+3
| | | | | | | | mcx was not updated according to changes in NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm/rpi: Enable dcacheAlexander Stein2015-08-12-1/+1
| | | | | | | | | Now that mailbox driver supports cache flush and invalidation, we can enable dcache. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZEAlexander Stein2015-08-12-0/+3
| | | | | | | | | | The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* sniper: Fastboot supportPaul Kocialkowski2015-08-12-0/+38
| | | | | | | | | | This adds support for the fastboot USB gadget, including flashing to the internal MMC and reboot to bootloader or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Update to use Kconfig for MUSB] Signed-off-by: Tom Rini <trini@konsulko.com>
* sniper: Pass serial number through ATAGPaul Kocialkowski2015-08-12-0/+1
| | | | | | | | | Now that the serial number is correctly defined, we can pass it to the kernel using the (legacy) ATAG method. It will be automatically passed via device-tree when enabled. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sniper: OMAP3 reboot mode supportPaul Kocialkowski2015-08-12-0/+3
| | | | | | | | | This adds support for the omap3 reboot mode mechanism and exports the reboot mode via an environment variable, that is used in the boot command to make it possible to boot from the recovery partition. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* LG Optimus Black (P970) codename sniper supportPaul Kocialkowski2015-08-12-0/+266
| | | | | | | | | | | | | | | | | | | | The LG Optimus Black (P970) codename sniper is a smartphone that was designed and manufactured by LG Electronics (LGE) and released back in 2011. It is using an OMAP3630 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. This port is aimed at running an Android version such as Replicant, the fully free Android distribution. However, support for upstream Linux with device-tree and common GNU/Linux distros boot commands could be added in the future. For more information about the journey to freeing this device, please read the series of blog posts at: http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add CONFIG_OF_SUPPORT] Signed-off-by: Tom Rini <trini@konsulko.com>
* lpc32xx: devkit3250: add spl build supportVladimir Zapolskiy2015-08-12-0/+53
| | | | | | | | | | | | The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND. All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: devkit3250: update of board configurationVladimir Zapolskiy2015-08-12-5/+87
| | | | | | | | | | | | This change adds more peripherals to Timll DevKit3250 board, namely MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C. Also the default serial console is changed to UART5, added an option to pass device tree blob by means of bootm, predefined environment variables are slightly extended and reserved space on NAND to store user defined U-boot environment. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* arm, at91: support for sam9260 based smartweb boardHeiko Schocher2015-08-12-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for the at91sam9260 based board smartweb from siemens. SPL is used without serial support, as this SoC has only 4k sram for running SPL. Here a U-Boot bootlog: RomBOOT > U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200) CPU: AT91SAM9260 Crystal frequency: 18.432 MHz CPU clock : 198.656 MHz Master clock : 99.328 MHz Watchdog enabled DRAM: 64 MiB WARNING: Caches not enabled NAND: 256 MiB In: serial Out: serial Err: serial Net: macb0 Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Heiko Schocher <hs@denx.de>
* spl, common, serial: build SPL without serial supportHeiko Schocher2015-08-12-0/+4
| | | | | | | | | This patch enables building SPL without CONFIG_SPL_SERIAL_SUPPORT support. Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Ensure we build arch/arm/imx-common on mx28] Signed-off-by: Tom Rini <trini@konsulko.com>
* port vexpress to use distro boot commandsDennis Gilmore2015-08-12-17/+17
| | | | | | | | remove options defined in the distro defaults add distro bot commands set scriptaddr value Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* Move setting CONFIG_BOOTP_VCI_STRING to before including the vexpress-common ↵Dennis Gilmore2015-08-12-3/+3
| | | | | | header Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* ARM: highbank: remove DRAM bank setupRob Herring2015-08-12-1/+2
| | | | | | | | | | | On the highbank platform the SoC's management controller firmware will probe the DRAM modules and populates the initial device tree with the correct values. Therefore the memory sizes in the DT are already correct, so remove U-Boot's DRAM bank setup so the memory node is not "fixed up" by u-boot. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-08-0/+12
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| * sunxi: Do not add a stdout-path alias to dts on boards without a serial portHans de Goede2015-08-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not add a bogus (pointing to a non existing serial port) stdout-path alias to dts on boards without a serial port. Note that we still define CONS_INDEX as this is used by the SPL where we do not use DM_SERIAL and thus CONFIG_REQUIRE_SERIAL_CONSOLE is not honored. We are getting away with this because the sun5i die actually has an uart0, which in the A13 package is not routed to the outside, so we are simply sending SPL bootup messages to the tx pin at the edge of the die, and they go no further from there... And sofar we only have one A13 board which does not have a serial port, all others do have a serial port. This kinda makes sense since the A13 is a much lower pincount package compared to all the other sunxi SoCs. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: nand: Add board configuration optionsPiotr Zierhoffer2015-08-08-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND. This commit also introduces the configurable options in Kconfig. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD usefulMarek Vasut2015-08-08-0/+4
| | | | | | | | | | | | | | | | Enable the mtdparts command and related options to make support for SPI NOR MTD useful in any way. With the mtdparts command in place, it is possible to use partition of the SPI NOR in U-Boot. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Fix LOADADDRMarek Vasut2015-08-08-2/+2
| | | | | | | | | | | | | | | | | | Setting LOADADDR to 0x8000 is a bad idea, it is very likely that some kind of overlap will happen. Move the LOADADDR 0x01000000 (16MiB from start of RAM) to make sure no overlap happens when loading kernel for example. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Enable CONFIG_SPI_FLASH_BARMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | | | | This is needed to access broken (read: Micron) SPI flashes which are larger than 16 MiB and don't correctly support 4-byte addressing. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL buildMarek Vasut2015-08-08-0/+2
| | | | | | | | | | | | | | We do not need full MTD support in the SPL build, it only adds size and is not usable in any way. Exclude it. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Zap incorrect config optionsMarek Vasut2015-08-08-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to disable support for partitions in the SPL, we can support partitions in SPL perfectly well. This is likely some remnant from old times, so just remove this configuration option. Moreover, the CRC32 chunk size doesn't have to be adjusted anymore, since both the GD and malloc area are in RAM by the time this CRC check can be used and there's plenty of space. Zap this abomination as well. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: config: Move SPL GD and malloc to RAMMarek Vasut2015-08-08-6/+8
| | | | | | | | | | | | | | | | | | | | | | Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: misc: Reset ethernet from OFMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Probe ethernet GMAC from OFMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | arm: socfpga: misc: Export bootmode into environment variableMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | | | | | | setenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from QSPIMarek Vasut2015-08-08-0/+9
| | | | | | | | | | | | | | Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Add support for booting from SD/MMCMarek Vasut2015-08-08-0/+14
| | | | | | | | | | | | | | | | | | | | Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Remove custom linker scriptMarek Vasut2015-08-08-3/+0
| | | | | | | | | | | | | | | | Remove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: spl: Merge spl_board_init() into board_init_f()Marek Vasut2015-08-08-1/+0
| | | | | | | | | | | | | | | | | | | | The code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: enable the Altera SDRAM controller driverDinh Nguyen2015-08-08-0/+5
| | | | | | | | | | | | | | Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* | arm: socfpga: Move generated files into qts subdirMarek Vasut2015-08-08-6/+6
|/ | | | | | | | | Move all the files generated by Quartus into the qts/ subdir of the board/altera/socfpga dir to make them explicitly separate from the generic U-Boot code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-112/+66
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| * exynos: Add support for springSimon Glass2015-08-05-0/+20
| | | | | | | | | | | | | | | | | | | | Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
| * video: Remove the old parade driverSimon Glass2015-08-05-4/+0
| | | | | | | | | | | | | | We have a new one which uses driver model and device tree configuration. Remove the old one. Signed-off-by: Simon Glass <sjg@chromium.org>
| * power: Remove old TPS65090 driversSimon Glass2015-08-05-2/+0
| | | | | | | | | | | | | | Remove the old drivers (both the normal one and the cros_ec one) now that we have new drivers that use driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5250-specific board codeSimon Glass2015-08-05-0/+2
| | | | | | | | | | | | | | Now that most exynos5250 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Drop old exynos5420-specific board codeSimon Glass2015-08-05-0/+2
| | | | | | | | | | | | | | | | Now that exynos5420 boards can use the generic exynos5 code, switch over to it and remove the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: config: Move common options to the common headers and tidy upSimon Glass2015-08-05-90/+39
| | | | | | | | | | | | | | | | | | | | Many options are duplicated on the exynos5 boards. Move these to the common files. Also some options are not used so can be removed. Tidy this up to make the files easier to maintain. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: Enable new features for exynos5 boardsSimon Glass2015-08-05-19/+6
| | | | | | | | | | | | | | Enable PMICs, regulators and the like so that new drivers will be made available. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra: Add p2371-0000 boardStephen Warren2015-08-06-0/+65
| | | | | | | | | | | | | | | | | | | | | | P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-05 08:25:14 +0000