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* | | mpc86xx: delete unused MPC86xx_DDR_SDRAM_CLK_CNTL definePaul Gortmaker2009-10-16-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | This is an orphaned legacy leftover that is just polluting the config file namespace. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/P1_P2_RDB: On-chip BootROM supportDipen Dudhat2009-10-16-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Chip BootROM support for P1 and P2 series RDB platforms. This patch is derived from latest On Chip BootROM support on MPC8536DS Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/P1_P2_RDB: NAND Boot SupportDipen Dudhat2009-10-16-7/+65
| |/ |/| | | | | | | | | | | | | | | NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | at91: Update MEESC board supportDaniel Gorsulowski2009-10-13-17/+8
| | | | | | | | | | | | | | | | | | | | | | This patch implements several updates: -disable CONFIG_ENV_OVERWRITE -add new hardware style variants and set the arch numbers appropriate -pass the serial# and hardware revision to the kernel -removed unused macros from include/configs/meesc.h -fixed multiline comment style Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
* | TI: OMAP3: Overo Tobi ethernet supportOlof Johansson2009-10-13-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | Add setup for ethernet on Tobi, allowing kernel/ramdisk to be loaded over tftp. This also refactors the smc911x driver to allow for detecting when the chip is missing. I.e. the detect_chip() function is called earlier and will abort gracefully when the Chip ID read returns all 1's. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Dirk Behme <dirk.behme@googlemail.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
* | TI OMAP3 Use arm init sequence to initialize i2cTom Rix2009-10-13-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes fixes an early i2c error. It appears that I2C is working because once a read or write error is detected, the omap24xx_i2c driver calls i2c_init inside its error handling check. While it is ok to attempt error handling this way, the boards must not depend on this side effect to initialize it's i2c. Instead of explicitly calling i2c_init for every board, use the generic arm initialization in lib_arm/board.c. By defining the config variable CONFIG_HARD_I2C, the omap3 i2c initialization is included in the init_sequence table. Run tested on Beagle. Compile tested on the omap3's Signed-off-by: Tom Rix <Tom.Rix@windriver.com> Acked-by: Dirk Behme <dirk.behme@googlemail.com>
* | Support for the OpenRD base boardSimon Kagstrom2009-10-13-0/+220
| | | | | | | | | | | | | | The implementation is borrowed from the sheevaplug board and the Marvell 1.1.4 code. Unsupported (or untested) is the SD card, PCIe and SATA. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
* | Add support for Eukrea CPU9260/CPU9G20 SBCTom Rix2009-10-13-0/+453
| | | | | | | | | | | | | | | | | | these boards are built around Atmel's AT91SAM9260/9G20 and have up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND and include a 10/100 Ethernet PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | Add support for Eukrea CPUAT91 SBCTom Rix2009-10-13-0/+228
| | | | | | | | | | | | | | | | | | CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII mode. Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | TI: DaVinci DM365: Minor config cleanupSandeep Paulraj2009-10-13-2/+0
| | | | | | | | | | | | | | | | | | | | The DM365 config was using the 'CONFIG_CMD_SAVEENV' flag. This is already included when we include the config_cmd_default.h header file. So this flag is removed. Also another flag to enable NAND functions was being enabled incorrectly. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | TI DaVinci: DM355: Config Cleanup and UpdateSandeep Paulraj2009-10-13-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following 1) Enables the NAND driver which is now available. 2) Enables the 'CONFIG_MTD_DEVICE' as without this the compilation will fail 3) We now have a safe place to store environment and defines an offset where this can be stored. This offset value is such that it is after the location where U-Boot is flashed using TI flash utilities. 4) Enables Bootdelay 5) Increases malloc() arena size. Manufacturers are coming out with NAND with large blocks sizes of upto 1 MiB. It has been noticed that as the block size of the NAND used is increased, if this particular value is not increased, the NAND driver will output out of memory errors. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | TI DaVinci: DM6446: Fix Compilation error in NAND modeSandeep Paulraj2009-10-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The Default mode that is built for the Davinci DVEVM happens to be the NOR mode. When we want to build for the NAND mode, we get a compilation error. This is overcome by defining the CONFIG_MTD_DEVICE flag in the NAND mode. The image built for NAND mode was successfully tested on the DaVinci DM6446 EVM. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | TI DaVinci: Remove references to SZ_xxSandeep Paulraj2009-10-13-19/+13
| | | | | | | | | | | | | | | | | | | | This patch removes the asm/sizes.h header file from being included in the DaVinci SOC configs. References to SZ_xx have been replaced by appropriate bit shifted values. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Wolfgang Denk <wd@denx.de>
* | Update all board to support new bbmiiphy driver (with multibus support)Luigi 'Comio' Mantellini2009-10-10-0/+74
|/ | | | | Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-5/+0
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| * p3mx: Remove serial relocation fixupsPeter Tyser2009-10-03-1/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Remove board-specific command table relocation fixupsPeter Tyser2009-10-03-1/+0
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | tqm5200: Correct comment and code in post_hotkeys_pressed.Detlev Zundel2009-10-08-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the code and the comment according to the original intent of doing an intensive memory test when PSC6_3 is pulled low on the STK52xx. Notably PORT_CONFIG will be overridden with this correct code now, so beware. The original code only worked by coincidence depending on the PORT_CONFIG setting from the header file. The new code was tested to ensure that the (undocumented) memory test still works on the STK52x. Signed-off-by: Detlev Zundel <dzu@denx.de> CC: Martin Krause <Martin.Krause@tqs.de> Minor white-space cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI APIBen Warren2009-10-04-38/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111 - cleaned up line lengths - modified all boards that override weak function in this driver - modified all eeprom standalone apps to work with new driver - updated blackfin standalone EEPROM app after testing Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-10-03-1/+0
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| * | ppc4xx: Add SDRAM detection for PMC440 boardsMatthias Fuchs2009-10-02-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch adds support to detect the amount of DDR2 SDRAM on PMC440 modules. Detection is done by probing through a list of available and supported hardware configurations from 1GByte down to 256MB. The static TLB entry is replaced by dynamically created entries. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-10-03-2/+2
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| * Blackfin: update default console= settingsMike Frysinger2009-09-30-1/+1
| | | | | | | | | | | | | | The Linux kernel has changed the way it numbers serial ports, so update the default command line to match it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bf533-ezkit: update env locationMike Frysinger2009-09-30-1/+1
| | | | | | | | | | | | | | | | The u-boot image has outgrown the current space and overflowed into the env sector. So move the env to the next available sector (we've already allocated the first few sectors anyways for u-boot). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-09-30-88/+187
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| * | On-chip ROM boot: MPC8536DS supportMingkai Hu2009-09-30-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | NAND boot: MPC8536DS supportMingkai Hu2009-09-30-18/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc8536: fix board config file line lengthMingkai Hu2009-09-30-68/+79
| | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | sbc8548: reclaim wasted sector in boot flashPaul Gortmaker2009-09-30-3/+17
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By nature of being based off the MPC8548CDS board, this board inherited an ENV_SIZE setting of 256k. But since it has a smaller flash device (8MB soldered on), it has a native sector size of 128k, and hence the ENV_SIZE was causing 2 sectors to be used for the environment. By removing the unused sector, we can push TEXT_BASE up closer to the end of address space and reclaim that sector for any other application. This also fixes the mismatch between TEXT_BASE and MONITOR_LEN reported by Kumar earlier. Since this board also supports the ability to boot off the 64MB SODIMM flash, this change is forward looking with that in mind; i.e. the settings for MONITOR_LEN and ENV_SIZE will work when the 512k sectors of the SODIMM flash are used for alternate boot in the future. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfieldsKim Phillips2009-09-26-16/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | sbc8349: tidy up Makefile to use new configuration script.Paul Gortmaker2009-09-25-0/+15
| | | | | | | | | | | | | | | | | | | | Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the board config header. This takes advantage of that for the sbc8349 board. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: mpc8360emds: Add QE USB device tree fixupsAnton Vorontsov2009-09-25-0/+2
| | | | | | | | | | | | | | | | With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUsAnton Vorontsov2009-09-25-2/+2
|/ | | | | | | | | This patch fixes various ethernet issues with gigabit links handling in U-Boot. The workarounds originally implemented by Kim Phillips for Linux kernel. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mucmc52, uc101: delete ata@3a00 node, if no CF card is detectedHeiko Schocher2009-09-25-0/+1
| | | | | | | | | | | U-Boot can detect if an IDE device is present or not. If not, and this new config option is activated, U-Boot removes the ATA node from the DTS before booting Linux, so the Linux IDE driver does not probe the device and crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc5200, mucmc52, uc101: config cleanupHeiko Schocher2009-09-25-504/+390
| | | | | | | | | | | | | | - As these boards are similiar, collect common config options in manroland/common.h and manroland/mpc52xx-common.h for mpc5200 specific common options for this manufacturer. - add OF support - update default environment Signed-off-by: Heiko Schocher <hs@denx.de> Minor edit of commit message. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add Elpida Memory Configuration to mpc5121ads BoardsMartha M Stan2009-09-25-2/+33
| | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor coding style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc512x: Streamlined fixed_sdram() init sequence.Martha M Stan2009-09-25-43/+32
| | | | | | | | | | | | | | | | | | | Signed-off-by: Martha M Stan <mmarx@silicontkx.com> Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-09-24-64/+148
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| * sbc85x0: tidy up Makefile to use new configuration script.Paul Gortmaker2009-09-24-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: allow enabling PCI via a make config optionPaul Gortmaker2009-09-24-10/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: update PCI/PCI-e support codePaul Gortmaker2009-09-24-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: correct local bus SDRAM size from 64M to 128MPaul Gortmaker2009-09-24-4/+38
| | | | | | | | | | | | | | | | | | | | | | The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: enable access to second bank of flashPaul Gortmaker2009-09-24-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * sbc8548: delete unused MPC8548CDS info carried over from portPaul Gortmaker2009-09-24-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Simplify the top makefile for P1_P2_RDB boardsKumar Gala2009-09-24-0/+13
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Simplify the top makefile for 36-bit config for P2020DSKumar Gala2009-09-24-0/+4
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DSKumar Gala2009-09-24-0/+4
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: simplify the top makefile for 36-bit config for mpc8536dsMingkai Hu2009-09-24-1/+1
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Fix LCRR_CLKDIV definesKumar Gala2009-09-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Peter Tyser <ptyser@xes-inc.com>
generated by cgit v1.1 at 2024-11-09 14:53:56 +0000