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* powerpc/mpc8536ds: Add USB support for MPC8536DSFanzc2011-10-09-0/+15
| | | | | | | Add EHCI controller and USB command definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8536ds: Add eSPI support for MPC8536DSXie Xiaobo2011-10-09-0/+14
| | | | | | | | | | 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8548cds: Update config filechenhui zhao2011-10-09-18/+26
| | | | | | | | | | | | | - Increase the size of malloc space. - Enable e1000 network card. - Show pci devices on startup. - Change the location of env address. - Use hwconfig to turn off ECC by default. [Kumar Gala] Fixed white space formating for CONFIG_EXTRA_ENV_SETTINGS Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc86xx: Disable translation for BAT setupBecky Bruce2011-10-09-50/+73
| | | | | | | | | | | | | | | | | We really shouldn't be overwriting bat registers with translation enabled, especially when we're executing code using one of them for translating the current instruction stream. Instead, disable address translation while doing the final BAT setup. In order to do this, setup_bats has to move back to asm code, because we require translation to be enabled to have a stack for C code. The yucky thing about that is that the assembler doesn't like ULL so we have to switch to using HIGH/LOW pairs for physical addresses that are > 32 bits in length. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8641hpcn: fix SRIO BAT configBecky Bruce2011-10-09-5/+0
| | | | | | | | There were duplicate (and conflicting) defines for the BATs used to cover SRIO. Drop the bogus set. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: CONFIG_ENABLE_36BIT_PHYS does not depend on CONFIG_PHYS_64BITTimur Tabi2011-10-09-3/+3
| | | | | | | | | | The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is capable of 36-bit physical addresses, even if such large addresses are not used. On two boards, this macro was enabled only when building a 36-bit image. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add support for interactive DDR programming interfaceYork Sun2011-10-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash. To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax: setenv ddr_interactive on After reset, U-boot prompts before initializing DDR controllers FSL DDR> The available commands are print print SPD and intermediate computed data reset reboot machine recompute reload SPD and options to default and recompute regs edit modify spd, parameter, or option compute recompute registers from current next_step to end next_step shows current next_step help this message go program the memory controller and continue with u-boot The first command should be "compute", which reads data from DIMM SPDs and board options, performs the calculation then stops before setting DDR controller. A user can use "print" and "edit" commands to view and modify anything. "Go" picks up from current step with any modification and compltes the calculation then enables the DDR controller to continue u-boot. "Recompute" does it over from fresh reading. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* board configs: drop NET_MULTI referencesMike Frysinger2011-10-05-483/+10
| | | | | | | Now that none of the core checks CONFIG_NET_MULTI, there's not much point in boards defining it. So scrub all references to it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* net: drop !NET_MULTI bcm570x/tigon3 driversMike Frysinger2011-10-05-3/+2
| | | | | | | | | | | These drivers have never been converted to NET_MULTI, and they are only used by one board (BMW). So drop the drivers until someone feels like rewriting them for NET_MULTI support. Rather than punting the BMW board completely, just disable net support in its board config. Seems to build fine without it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* km_arm: enable POST for these boardsValentin Longchamp2011-10-05-0/+6
| | | | | | | | | | | | The current km_arm boards have a Power-On test jumper. When this jumper is set, this triggers some Power-On tests on the board. This patch enables the support of this jumper for starting the memory_regions test when the jumper is set. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Prafulla Wadaskar <prafulla@marvell.com>
* km_arm: change CONFIG_SYS_TEXT_BASE to end of RAMValentin Longchamp2011-10-05-1/+1
| | | | | | | | | This allows to test a larger part of the RAM in the memory tests. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Heiko Schocher <hs@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-10-04-290/+1867
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
| * powerpc/85xx: Add support for setting up RAID engine liodns on P5020Kumar Gala2011-10-03-0/+1
| | | | | | | | | | | | | | | | | | Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Refactor some defines out of corenet_ds.hKumar Gala2011-10-03-8/+16
| | | | | | | | | | | | | | | | | | | | | | Move some SoC/board specific defines out of corenet_ds.h and into the corresponding P3041DS/P4080DS/P5020.h. We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060 SoC/reference board does not have these devices and it will share the same board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/p4080: Add support for secure boot flowRuchika Gupta2011-10-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASHRuchika Gupta2011-10-03-2/+13
| | | | | | | | | | Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
| * powerpc/p2041rdb: set sysclk according to status of physical switch SW1Shaohui Xie2011-10-03-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software need to read the SW1 status to decide what the sysclk needs. SW1[8~6] : frequency 0 0 1 : 83.3MHz 0 1 0 : 100MHz others: 66.667MHz Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driverYork Sun2011-09-29-0/+16
| | | | | | | | | | | | | | | | | | | | Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c. The unified driver can initialize data using DDR controller. No need to use DMA if just to initialze for ECC. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Enable CMD_REGINFO on corenet boardsKumar Gala2011-09-29-0/+1
| | | | | | | | | | | | | | Useful for various debug to know how various regsters might be set in a human readable form. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Fix USB protocol definitions for P1020RDBRamneek Mehresh2011-09-29-1/+4
| | | | | | | | | | | | | | | | | | USB protocol macros (CONFIG_USB_EHCI ...) to be included only when CONFIG_HAS_FSL_DR_USB is defined for a board. Presence of USB DR controller should be declared along with the underlying protocol used in the controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/p2041rdb: Add ethernet support on P2041RDB boardMingkai Hu2011-09-29-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board. The five dTSEC can be routed to two on-board RGMII phy, three on-board SGMII phy or four SGMII phy on SGMII riser card according to different serdes protocol configuration and board lane configuration. Also updated the device tree to direct the Fmac MAC to the correct PHY. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add networking support to P1023RDSRoy Zang2011-09-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add FMan ethernet support to P4080DSAndy Fleming2011-09-29-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS. The board supports add-on cards for SGMII and XAUI functionality. Which slots on the board these cards are in is a function of the SERDES option selected and muxes on the board. Additionally because of the high-configurablity which MDIO bus one is connected to is "selected" via an FPGA register. We create dummy MDIO bus for the phy layer and hide the mux manipulation in this dummy layer. Add fman fdt helper function in board common code it'll be used by several freescale boards that do various muxing of the MDIO signals based on which controller/interface one is trying to talk to. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add NAND/NAND_SPL support to P1010RDBDipen Dudhat2011-09-29-0/+59
| | | | | | | | | | | | | | | | | | And various defines to enable NAND support and NAND spl code for the P1010RDB platform. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add basic support for P1010RDBPoonam Aggrwal2011-09-29-0/+706
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support for new P102x/P2020 RDB style boardsLi Yang2011-09-29-0/+984
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following boards share a common design but with minor variations between them: P1020MSBG-PC P1020RDB-PC P1020UTM-PC P1021RDB-PC P1024RDB P1025RDB P2020RDB-PC The P1020RDB-PC shares its roots in the existing P1020RDB board design, however uses DDR3 instead of DDR2. P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK. Key features on these boards include: * DDR3 * NOR flash * NAND flash (on RDB's only) * SPI flash (on RDB's only) * SDHC/MMC card slot * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) * PCIE slot and mini-PCIE slots As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM is used to store SPD data. In case of absent or corrupted SPD, falling back to timing data embedded in the source code will be used. Raw timing data is extracted from DDR chip datasheet. Different speeds of DDR are supported with this approach. ODT option is forced to fit this set of boards, again because they don't have regular DIMMs. CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification for writing timing. VSC firmware Address is defined by default in config file for eTSEC1. SD width is based off DIP switch. DIP switch is detected on the board by reading i2c bus and setting the appropriate mux values. Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have pins multiplexing. QE function needs to be disabled to access Nor Flash and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
| * powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macrosTimur Tabi2011-09-29-277/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | microblaze: Enable FDT/FIT supportMichal Simek2011-10-03-0/+5
| | | | | | | | | | | | Enable FDT and FIT support. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | microblaze: Remove address offset for uart16550Michal Simek2011-10-03-1/+1
| | | | | | | | | | | | | | U-Boot BSP handle 0x3 offset for big endian systems. Little endian Microblaze systems don't use any offset. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | microblaze: Do not select NFS for platforms without ethernetMichal Simek2011-10-03-0/+2
| | | | | | | | | | | | | | Undefined network functionality for systems without ethernet and disable NFS support. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | sbc82xx: delete support for obsolete SBC8240/SBC8260Paul Gortmaker2011-10-01-1449/+3
| | | | | | | | | | | | | | | | | | | | The EST SBC8260 is over 10 years old, and the SBC8240 older than that. With the tiny amount of RAM (by today's standards), there really isn't anyone interested in running the latest U-boot on these EOL products anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> CC: jon.diekema@smiths-aerospace.com
* | Merge branch 'post' of git://git.denx.de/u-boot-blackfinWolfgang Denk2011-10-01-5/+17
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'post' of git://git.denx.de/u-boot-blackfin: Blackfin: uart: implement loop callback for post Blackfin: bf537-stamp/bf548-ezkit: update POST flash block range Blackfin: post: generalize led/button tests with GPIOs Blackfin: bf537-stamp: drop uart/flash post tests Blackfin: post: drop custom test list Blackfin: bf537-stamp: convert to gpio post hotkey
| * | Blackfin: bf537-stamp/bf548-ezkit: update POST flash block rangeMike Frysinger2011-09-29-4/+4
| | | | | | | | | | | | | | | | | | | | | Update the define names for the new common code, and improve the range used on the bf548-ezkit. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: post: generalize led/button tests with GPIOsMike Frysinger2011-09-29-0/+12
| | | | | | | | | | | | | | | | | | Make it easy for any Blackfin board to enable led/push button tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: post: drop custom test listMike Frysinger2011-09-29-1/+0
| | | | | | | | | | | | | | | | | | | | | The few tests that are Blackfin-specific have been migrated to common code or been rewritten with the existing "bsp-specific" defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: bf537-stamp: convert to gpio post hotkeyMike Frysinger2011-09-29-0/+1
| |/ | | | | | | | | | | | | No need for our custom implementations now that common code supports the generic gpio layer. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | EfikaSB: Add preliminary EfikaSB supportMarek Vasut2011-09-30-0/+4
| | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* | vision2: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | | | | | Let common code set the machine ID. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | zmx25: Place machine ID into board configFabio Estevam2011-09-30-0/+1
| | | | | | | | | | | | | | Let common code set the machine ID. Cc: Matthias Weisser <weisserm@arcor.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx53evk: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* | mx53ard: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx53smd: Place machine ID into board configFabio Estevam2011-09-30-1/+3
| | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx53loco: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <jason.hui@linaro.org>
* | mx51evk: Place machine ID into board configFabio Estevam2011-09-30-0/+1
| | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx31_litekit: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx31ads: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx25pdk: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx31pdk: Place machine ID into board configFabio Estevam2011-09-30-0/+2
| | | | | | | | | | | | Let common code set the machine ID. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx31_litekit: Remove dram_init_banksize()Fabio Estevam2011-09-30-1/+1
| | | | | | | | | | | | As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | EfikaMX: Adjust undocumented magic constant in config fileMarek Vasut2011-09-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This magic constant with zero documentation, when it's last 8 bits are set to 0x45, configures correctly the PERCLK dividers. Therefore the I2C operates correctly when divider computed from PERCLK. Note: This constant is written to CBCDR register in arch/arm/cpu/armv7/mx5/lowlevel_init.S, but it's written only once. The register is accessed three more times in the file, with different values written to it each time. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
generated by cgit v1.1 at 2024-11-07 11:04:37 +0000