summaryrefslogtreecommitdiff
path: root/include/configs
Commit message (Collapse)AuthorAgeLines
* mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov2008-10-21-0/+2
| | | | | | | | | | With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add ELBC NAND support for the MPC837XEMDS boardsAnton Vorontsov2008-10-21-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-21-0/+3
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov2008-10-21-0/+2
| | | | | | | | | | This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: mpc8360emds: rework LBC SDRAM setupAnton Vorontsov2008-10-21-14/+11
| | | | | | | | | | | | | | | | | | | Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes it difficult to use (b/c then the memory is discontinuous and there is quite big memory hole between the DDR/SDRAM regions). This patch reworks LBC SDRAM setup so that now we dynamically place the LBC SDRAM near the DDR (or at 0x0 if there isn't any DDR memory). With this patch we're able to: - Boot without external DDR memory; - Use most "DDR + SDRAM" setups without need to support for sparse/discontinuous memory model in the software. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-293/+744
|\
| * ppc4xx: Add GDSys neo 405EP board supportDirk Eibach2008-10-21-0/+231
| | | | | | | | | | Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Update configs for Netstal boardsNiklaus Giger2008-10-21-275/+292
| | | | | | | | | | | | | | | | | | | | I reorganized my config files, putting the common stuff into netstal-common.h (got the idea by looking a amcc-common.h from Stefan). Added stuff to boot the new powerpc linux via NFS (only tested with HCU4). Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-18/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | TQM8260: environment in flash instead EEPROM, baudrate 115kWolfgang Denk2008-10-21-20/+10
|/ | | | | | | | | | | | | | Several customers have reported problems with the environment in EEPROM, including corrupted content after board reset. Probably the code to prevent I2C Enge Conditions is not working sufficiently. We move the environment to flash now, which allows to have a backup copy plus gives much faster boot times. Also, change the default console initialization to 115200 bps as used on most other boards. Signed-off-by: Wolfgang Denk <wd@denx.de>
* mgcoge: add redundant environment sectorHeiko Schocher2008-10-18-0/+5
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* mgsuvd: update size of environmentHeiko Schocher2008-10-18-3/+1
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+3
| | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+24
| | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* Make pixis_set_sgmii more general to support MPC85xx boards.Liu Yu2008-10-18-0/+3
| | | | | | | | | | | | The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-1/+2
| | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xx: Enable interrupt and setexpr commands on Freescale 85xx boardsKumar Gala2008-10-18-0/+18
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mgsuvd: fix compiler warning when using soft_i2c driverHeiko Schocher2008-10-18-9/+9
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* mgsuvd: fix coding styleHeiko Schocher2008-10-18-6/+4
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* mgcoge: added CONFIG_FIT to support the new u-boot image formatHeiko Schocher2008-10-18-0/+1
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-35597/+35597
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mgsuvd, mgcoge: added BOOTCOUNT feature.Heiko Schocher2008-10-18-0/+4
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* mgcoge, mgsuvd: added support for the IVM EEprom.Heiko Schocher2008-10-18-0/+12
| | | | | | | | The EEprom contains some Manufacturerinformation, which are read from u-boot at boot time, and saved in same hush shell variables. Signed-off-by: Heiko Schocher <hs@denx.de>
* I2C: adding new "i2c bus" Command to the I2C Subsystem.Heiko Schocher2008-10-18-0/+2
| | | | | | | With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by: Heiko Schocher <hs@denx.de>
* mgcoge, mgsuvd: add board specific I2C deblocking mechanism.Heiko Schocher2008-10-18-0/+2
| | | | | | | | | | | | | | | | | | | | As documented in doc/I2C_Edge_Conditions, adding a board specific deblocking mechanism via CFG_I2C_INIT_BOARD for the mgcoge and mgsuvd board. This code was originally written by Keymile in association with Anatech and Atmel in 1998. The Code toggels the SCL until the SCA line goes to HIGH (max. 16 times). And after this, a start condition is sent. This is another approach to deblock the I2C Bus. The soft I2C driver actually sends 9 clocks with SDA High, and then a stop at the end, to deblock the I2C Bus. Maybe we should use the approach from Keymile as the new standard? Signed-off-by: Heiko Schocher <hs@denx.de>
* mgcoge, mgsuvd: add DTT (LM75) support.Heiko Schocher2008-10-18-0/+18
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* mgcoge, mgsuvd: added EEprom support.Heiko Schocher2008-10-18-0/+15
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* mgcoge, mgsuvd: add I2C support.Heiko Schocher2008-10-18-0/+68
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* Change UEC PHY interface to RGMII on MPC8568MDSHaiying Wang2008-10-18-2/+2
| | | | | | | | | | | | | | Change UEC phy interface from GMII to RGMII on MPC8568MDS board Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed, but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable. Now both UEC1 and UEC2 can work properly under u-boot. It is also in consistent with the kernel setting for 8568 UEC phy interface. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Remove unwanted ';' at end of define.Selvamuthukumar2008-10-14-12/+12
| | | | | | | | | | | | | Currently this is not creating any problem. But it will result in compilation error when used as below. printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2); Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> continuation of the theme based on git grep "^#define CFG_.*;$" include/ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Remove unused CFG_EEPROM_PAGE_WRITE_ENABLE referencesPeter Tyser2008-10-14-66/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* sh: rsk7203: Add smc911x driver support to board config fileNobuhiro Iwamatsu2008-10-14-0/+5
| | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-10-13-14/+36
|\
| * Merge branch 'master' of ssh://10.10.0.7/home/wd/git/u-boot/masterWolfgang Denk2008-10-12-7/+3
| |\
| | * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2008-10-12-7/+3
| | |\
| | | * i.MX31: switch to CFG_HZ=1000Guennadi Liakhovetski2008-10-08-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the standard CFG_HZ=1000 value, while at it, minor white-space cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads, provides 2% or 0.4% precision depending on the CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s boot-delay. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| * | | Merge branch 'master' of ssh://10.10.0.7/home/wd/git/u-boot/masterWolfgang Denk2008-10-12-7/+30
| |\ \ \ | | |/ /
| | * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-12-4/+18
| | |\ \
| | | * | MPC8572DS: Fix compile warningsKumar Gala2008-10-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following compile warnings: cmd_i2c.c:112: warning: missing braces around initializer cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]') Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | | * | Remove redundant #define for MPC8536DSHaiying Wang2008-10-07-1/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | | * | Add ID EEPROM support for MPC8572DSHaiying Wang2008-10-07-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for system information like mac addresses etc. This patch enables it. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | | * | Minor fixes for I2C address on MPC8572DSHaiying Wang2008-10-07-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1 according to the board spec, and adds the 2nd i2c bus offset. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | | * | Fix the incorrect DDR clk freq reporting on 8536DSJason Jin2008-10-07-1/+1
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| | * | mpc83xx: don't disable autobootKim Phillips2008-09-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bootdelay set to -1 'permanently' disables autobooting, even if bootcmd is specified. Change to a positive value to allow autobooting when a bootcmd is set. Reported-by: Coray Tate <Coray.Tate@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | mpc83xx: add h/w flash protection to board configsKim Phillips2008-09-24-0/+9
| | |/ | | | | | | | | | | | | | | | | | | | | | the operating system may leave flash in a h/w locked state after writing. This allows u-boot to continue to write flash by enabling h/w unlocking by default. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | TQM5200: enable support for ATAPI devicesWolfgang Denk2008-10-01-0/+3
| |/ | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Update DU440 configMatthias Fuchs2008-10-10-2/+4
|/ | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* socrates: change default mtest address rangeAnatolij Gustschin2008-09-22-2/+2
| | | | | | | | Running mtest command on socrates without specifying an address range crashes the board. This patch changes default mtest address range to prevent this behavior. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* socrates: fix SPD EEPROM addressAnatolij Gustschin2008-09-22-1/+1
| | | | | | | | | Commit be0bd8234b9777ecd63c4c686f72af070d886517 changed SPD EEPROM address to 0x51 and DDR SDRAM detection stopped working. Change this address back to 0x50. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* ADS5121: fix typo in "rootpath" default settingWolfgang Denk2008-09-18-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
generated by cgit v1.1 at 2024-12-22 04:18:13 +0000