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* ppc4xx: Minor updates for DU440 boardsMatthias Fuchs2008-03-31-10/+6
| | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revisionStefan Roese2008-03-28-0/+1
| | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch displays the current configuration upon bootup and changes the PCIe init loop, to only initialize the availabel PCIe slots. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable ECC on LWMON5Stefan Roese2008-03-27-5/+1
| | | | | | | | | | | Since all ECC related problems seem to be resolved on LWMON5, this patch now enables ECC support. We have to write the ECC bytes by zeroing and flushing in smaller steps, since the whole 256MByte takes too long for the external watchdog. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Updates to Korat-specific codeLarry Johnson2008-03-27-22/+43
| | | | | | | | | | | | | | | | This patch contains updates for changes for the Korat PPC440EPx board. These changes include: (1) Support for "permanent" and "upgradable" copies of U-Boot, as described in the new "doc/README.korat" file; (2) a new memory map for the registers in the board's CPLD; (3) a revised format for manufacturer's data in serial EEPROM; and (4) changes to track updates to U-Boot for the Sequoia board. Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Add fdt support to Prodrive alprStefan Roese2008-03-27-1/+12
| | | | | | | | Since this board will probably be ported to arch/powerpc in the near future, we add device tree support now. This way we are "ready" for arch/powerpc from now on. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable cache support on the ALPR boardPieter Voorthuijsen2008-03-27-0/+1
| | | | Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
* ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"Stefan Roese2008-03-27-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Glacier 406GT eval board supportStefan Roese2008-03-27-11/+114
| | | | | | | | | | | | | | This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-03-27-0/+32
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| * FSL: Clean up board/freescale/common/MakefileJon Loeliger2008-03-26-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each file that can be built here now follows some CONFIG_ option so that they are appropriately built or not, as needed. And CONFIG_ defines were added to various board config files to make sure that happens. The other board/freescale/*/Makefiles no longer need to reach up and over into ../common to build their individually needed files any more. Boards that are CDS specific were renamed with cds_ prefix. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-0/+17
| | | | | | | | | | | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ata: make the ata_piix driver using new SATA frameworkDave Liu2008-03-26-24/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | original ata_piix driver is using IDE framework, not real SATA framework. For now, the ata_piix driver is only used by x86 sc520_cdp board. This patch makes the ata_piix driver use the new SATA framework, so - remove the duplicated command stuff - remove the CONFIG_CMD_IDE define in the sc520_cdp.h - add the CONFIG_CMD_SATA define to sc520_cdp.h Signed-off-by: Dave Liu <daveliu@freescale.com>
* | ata: merge the ata_piix driverDave Liu2008-03-26-1/+0
|/ | | | | | | | move the cmd_sata.c from common/ to drivers/ata_piix.c, the cmd_sata.c have some part of ata_piix controller drivers. consolidate the driver to have better framework. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Merge branch 'new-image' of git://www.denx.de/git/u-boot-testingBartlomiej Sieka2008-03-26-0/+6
|\ | | | | | | | | | | | | | | | | Conflicts: common/cmd_bootm.c cpu/mpc8xx/cpu.c Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
| * [new uImage] Enable new uImage support for the pcs440ep board.Bartlomiej Sieka2008-03-20-0/+6
| | | | | | | | Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
* | 83xx/fdt_support: let user specifiy FSL USB Dual-Role controller roleAnton Vorontsov2008-03-25-0/+2
| | | | | | | | | | | | | | | | | | Linux understands "host" (default), "peripheral" and "otg" (broken). Though, U-Boot doesn't restrict dr_mode variable to these values (think of renames in future). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clockJoe D'Abbraccio2008-03-25-1/+1
| | | | | | | | | | | | | | | | | | With the original value of 1/2 clock cycle delay, the system ran relatively stable except when we run benchmarks that are intensive users of memory. When I run samba connected disk with a HDBENCH test, the system locks-up or reboots sporadically. Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
* | mpc83xx: Set PCI I/O bus-address base to zero.Scott Wood2008-03-25-5/+5
| | | | | | | | | | | | | | | | | | | | The device trees for these boards describe PCI I/O as starting from address zero from the device's perspective. Placing I/O elsewhere may cause problems with certain PCI boards, and may cause problems with Linux. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | mpc83xx: MPC8360E-RDK: use 33.3(3)MHz CLKIN/SYS_CLKAnton Vorontsov2008-03-25-2/+2
| | | | | | | | | | | | | | At least on the "33MHz Pilot" board crystal is actually 33.3MHz. This patch fixes "system time drifting" problem. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | mpc83xx: MPC8360E-RDK: define CONFIG_OF_STDOUT_VIA_ALIASAnton Vorontsov2008-03-25-0/+1
| | | | | | | | | | | | This is needed to update /choosen/linux,stdout-path properly. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | mpc83xx: MPC8360E-RDK: add dhcp commandAnton Vorontsov2008-03-25-4/+3
| | | | | | | | | | | | | | Plus modify environment to use it and remove bootfile env variable, it is internal and CONFIG_BOOTFILE is used for these purposes. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | mpc83xx: MPC8360E-RDK: rework ddr setup, enable eccAnton Vorontsov2008-03-25-12/+36
| | | | | | | | | | | | | | | | Current DDR setup easily causes memory corruption, this patch fixes it. Also fix TIMING_CFG0_MRS_CYC definition. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | mpc83xx: MPC8360E-RDK: add support for NANDAnton Vorontsov2008-03-25-0/+24
| | | | | | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | mpc83xx: MPC8360E-RDK: use RGMII_RXID interface modeAnton Vorontsov2008-03-25-2/+2
| | | | | | | | | | | | This is needed for BCM PHYs to work on this board. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boardsAnton Vorontsov2008-03-25-0/+1
| | | | | | | | | | | | This is primarily for the early console support. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | 83xx: initialize serdes for MPC837XRDB boardsAnton Vorontsov2008-03-25-0/+6
| | | | | | | | | | | | | | | | On the MPC8377ERDB: 2 SATA and 2 PCI-E. On the MPC8378ERDB: 2 PCI-E On the MPC8379ERDB: 4 SATA Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | 83xx: nand support for MPC837XRDB boardsAnton Vorontsov2008-03-25-0/+19
| | | | | | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* | Enable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS.Jerry Van Baren2008-03-25-0/+1
| | | | | | | | | | Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc8323erdb: remove RTC and add EEPROMMichael Barkowski2008-03-25-3/+4
| | | | | | | | | | | | | | There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc8323erdb: Improve the system performanceMichael Barkowski2008-03-25-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* | mpc8323erdb: use readable DDR config macrosMichael Barkowski2008-03-25-8/+42
| | | | | | | | | | | | | | Use available shift/mask macros to define DDR configuration. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* | 83xx: Add Vitesse VSC7385 firmware uploadingTimur Tabi2008-03-25-65/+139
| | | | | | | | | | | | | | | | | | | | Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. Cleaned up the board header files to make selecting the VSC7385 easier to control. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_TJerry Van Baren2008-03-26-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These defines embedded the u-boot env variables and/or the bd_t structure in the fdt blob. The conclusion of discussion on the u-boot email list was that embedding these in the fdt blob is not useful: there are better ways of passing the data (in fact, the fdt blob itself replaces the bd_t struct). The only board that enables these is the stxxtc and they don't appear to be used by linux. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* | 8xx : Add OF support to Adder875 board port - resubmitBryan O'Donoghue2008-03-25-0/+6
| | | | | | | | Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
* | TQM5200B: update MTD partition layoutMartin Krause2008-03-19-5/+16
| | | | | | | | | | | | | | | | - insert partition for dtb blob to TQM5200B MTD layout - set env variables dependent on the configured board (TQM5200 or TQM5200B) Signed-off-by: Martin Krause <martin.krause@tqs.de>
* | The patch introduces the alternative configuration of the log buffer for the ↵Yuri Tikhonov2008-03-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5). To enable this, alternative, configuration the U-Boot board configuration file for lwmon5 includes the definitions of alternative addresses for header (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* | Add support for the lwmon5 board reset via GPIO58.Yuri Tikhonov2008-03-18-0/+2
| | | | | | | | | | Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* | The patch adds new POST tests for the Lwmon5 board. These are:Yuri Tikhonov2008-03-18-4/+88
| | | | | | | | | | | | | | | | | | | | | | * External Watchdog test; * dsPIC tests; * FPGA test; * GDC test; * Sysmon tests. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-blackfinWolfgang Denk2008-03-18-56/+27
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| * | Blackfin: BF537-stamp: drop board-specific flash driver for CFIMike Frysinger2008-03-15-4/+5
| | | | | | | | | | | | | | | | | | | | | The parallel flash on the BF537-STAMP is CFI compliant, so there is no need for the board specific driver at all. Just use the common CFI driver. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: convert BFIN_CPU to CONFIG_BFIN_CPUMike Frysinger2008-03-15-52/+22
| |/ | | | | | | | | | | | | | | Stop tying things to the processor that should be tied to other defines and change BFIN_CPU to CONFIG_BFIN_CPU so that it can be used in the build system to select the -mcpu option. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/masterWolfgang Denk2008-03-16-3/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/rtc/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | mgcoge: update configurationHeiko Schocher2008-03-16-3/+2
| |/ | | | | | | | | | | Fix configuration for mgcoge board Signed-off-by: Heiko Schocher <hs@denx.de>
* | Conding style cleanupWolfgang Denk2008-03-16-1/+0
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval boardStefan Roese2008-03-15-22/+46
| | | | | | | | | | | | | | This patch adds USB OHCI support to the Canyonlands board port. It also enables EXT2 support. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-8/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add AMCC Canyonlands support (460EX) (2/3)Stefan Roese2008-03-15-0/+470
| | | | | | | | | | | | | | This patch adds support for the AMCC Canyonlands 460EX evaluation board. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add 405GPr based MCU25 board config fileNiklaus Giger2008-03-15-0/+362
| | | | | | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* | ppc4xx: HCU4/5. Use FLASH_CFI_LEGACYNiklaus Giger2008-03-15-9/+23
|/ | | | | | | Cleanup: Remove custom flash driver for 8 bit boot-eprom and replace it with the FLASH_CFI_LEGACY et al. config options. Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk2008-03-08-4/+4
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