| Commit message (Collapse) | Author | Age | Lines |
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For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Bridge, ICH-5, ICH-6 and ICH-7.
Implementation:
1. Code is divided in to two files. All functions, which are
controller specific are kept in "drivers/ata_piix.c" file and
functions, which are not controller specific, are kept in
"common/cmd_sata.c" file.
2. Reading and Writing from the S-ATA drive is done using PIO method.
3. Driver can be configured for 48-bit addressing by defining macro
CONFIG_LBA48, if this macro is not defined driver uses the 28-bit
addressing.
4. S-ATA read function is hooked to the File system, commands like
ext2ls and ext2load file can be used. This has been tested.
5. U-Boot command "SATA_init" is added, which initializes the S-ATA
controller and identifies the S-ATA drives connected to it.
6. U-Boot command "sata" is added, which is used to read/write, print
partition table and get info about the drives present. This I have
implemented in same way as "ide" command is implemented in U-Boot.
7. This driver is for S-ATA in native mode.
8. This driver does not support the Native command queuing and
Hot-plugging.
Signed-off-by: Mushtaq Khan <mushtaq_k@procsys.com>
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The attached patch fixes the compile of the JSE board in the
denx git as of 14 may 2007. It is an extremely simple patch,
it just adds the missing define of CFG_SYSTEMACE_WIDTH.
Fix to compile JSE against 20070514 git of u-boot
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Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
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This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.
Signed-off-by: Stefan Roese <sr@denx.de>
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-add pci_pre_init() for pci interrupt fixup code
-disable phy sleep mode via reset_phy() function
-use correct io accessors
-cleanup
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
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Now CONFIG_440 has to be defined in all PPC440 board config files.
Signed-off-by: Stefan Roese <sr@denx.de>
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- Introduced dedicated switches for building 440 and 405 images required
for 440-specific machine instructions like 'rfmci' etc.
- Exception vectors moved to the proper location (_start moved away from
the critical exception handler space, which it occupied)
- CriticalInput now serviced (with default handler)
- MachineCheck properly serviced (added a dedicated handler and return
subroutine)
- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
unhandled and those not relevant for 4xx were eliminated)
- Eliminated Linux leftovers, removed dead code
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds initial support for the Liebherr lwmon5 board euqipped
with an AMCC 440EPx PowerPC.
Signed-off-by: Stefan Roese <sr@denx.de>
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The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
is extended with the default GPIO output state (level).
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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e600 does not have a bootpg restriction.
Move the version string to beginning of image at fff00000.
Resetvec.S is not needed.
Update flash copy instructions.
Add tftpflash env variable
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Stefan Roese <sr@denx.de>
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This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.
Signed-off-by: Stefan Roese <sr@denx.de>
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With the updated 44x DDR2 driver the Luan board now supports
ECC generation and checking.
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
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Enable redundant environment, add a MTD partition for it; also add env.
variable command for passing MTD partitions to the kernel command line.
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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Allow passing longer command line to the kernel - useful especially
for passing MTD partition layout.
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A
have a page write capability of two bytes", and "This device offers fast (1ms)
byte write". Add 3ms of extra delay.
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit
008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
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This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.
Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.
Signed-off-by: Stefan Roese <sr@denx.de>
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