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* am335x: enable falcon boot mode for mmc (raw and fat) and nandPeter Korsgaard2013-06-07-3/+27
| | | | | | | | | | | | | | | | Jump into full u-boot mode if a 'c' character is received on the uart. We need to adjust the spl bss/malloc area to not overlap with the loadaddr of the kernel (sdram + 32k), so move it past u-boot instead. For raw mmc, we store the kernel parameter area in the free space after the MBR (if used). For nand, we use the last sector of the partition reserved for u-boot. This also enables the spl command in the full u-boot so the kernel parameter area snapshot can be created. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* devkit8000: Add SPL_OS for MMC supportTom Rini2013-06-07-0/+8
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2013-06-07-0/+2
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| * ARM: bcm2835: add simplefb DT node during bootz/mStephen Warren2013-06-05-0/+2
| | | | | | | | | | | | | | | | | | | | Add a DT simple-framebuffer node to DT when booting the Linux kernel. This will allow the kernel to inherit the framebuffer configuration from U-Boot, and display a graphical boot console, and even run a full SW- rendered X server. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Simon Glass <sjg@chromium.org>
* | am33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>Tom Rini2013-06-06-9/+6
| | | | | | | | | | | | | | | | | | | | The location of valid scratch space is dependent on SoC, so move that there. On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR. On am33xx/ti814x we want to use what the ROM defines as "public stack" which is the area after our defined download image space. Correct the comment about and location of CONFIG_SPL_TEXT_BASE. Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-05-6/+24
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| * | am33xx: Correct NON_SECURE_SRAM_START/ENDTom Rini2013-06-04-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to Sricharan's cleanup of the boot parameter saving code, we did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a problem that the address was pointing to the middle of our running SPL. Correct to point to the base location of the download image area. Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being used. As part of correcting these tests, make use of the fact that we've always been placing our stack outside of the download image area (which is fine, once the downloaded image is run, ROM is gone) so correct the max size test to be the ROM defined top of the download area to where we link/load at. Signed-off-by: Tom Rini <trini@ti.com> --- Changes in v2: - Fix typo noted by Peter Korsgaard
* | | Merge branch 'tpm' of git://git.denx.de/u-boot-x86Tom Rini2013-06-05-4/+5
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| * | | tpm: Reorganize the I2C TPM driverTom Wai-Hong Tam2013-06-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does a similar code reogranzation from http://patchwork.ozlabs.org/patch/132179/ which is based on an old version of code (fdt support and bus selection still not in). It merges this tidy-up on top of the recent code. It does not make any logical change. tpm.c implements the interface defined in tpm.h based on underlying LPC or I2C TPM driver. tpm.c and the underlying driver communicate throught tpm_private.h. Note: Merging the LPC driver with tpm.c is left to future patches. Change-Id: Ie1384f5f9e3935d3bc9a44adf8de80c5a70a5f2b Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: config: Reflect the name changes of LPC TPM configsTom Wai-Hong Tam2013-06-03-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new name is more aligned with Linux kernel's naming of TPM driver. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | at91: Correct CONFIG_AUTOBOOT_PROMPT definition for pm9263Simon Glass2013-06-04-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | This is not currently used, since autoboot is not enabled for this board, but the string is missing a parameter. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-05-31-2/+0
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| * | mtd: resync with Linux-3.7.1Sergey Lapin2013-05-31-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
* | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-1006/+113
|\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * | | powerpc/b4860qds: Add LAW Target ID and Create LAW entry for MapleShaveta Leekha2013-05-24-0/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.hPoonam Aggrwal2013-05-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/p5040: enable PBL tool supportShaohui Xie2013-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.hYork Sun2013-05-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | T4240/ramboot: enable PBL tool for T4240Shaohui Xie2013-05-24-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-14/+29
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| | * | T4240/net: use QSGMII card PHY address by defaultShaohui Xie2013-05-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-14-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc: Add T4160QDSYork Sun2013-05-14-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160QDS shares the same platform as T4240QDS. T4160 is a low power version of T4240, with eight e6500 cores, two DDR3 controllers, and slightly different SerDes protocols. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: Move SoC define into boards.cfgYork Sun2013-05-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC variants supported on the same board. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: Add voltage ID supportYork Sun2013-05-14-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: fix XAUI card PHY addressShaohui Xie2013-05-14-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4240qds: Fix SPI flash typeShaohui Xie2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240QDS uses a SST instead of SPANSION SPI flash. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-958/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-blackfin into ↵Tom Rini2013-05-14-27/+49
| |\ \ \ | | |/ / | |/| | | | | | powerpc-eldk53-warning-fixes
| | * | bfin: Move gpio support for bf54x and bf60x into the generic driver folder.Sonic Zhang2013-05-13-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx. A lot of machine macros are used to accomodate both code in one gpio driver. This patch split the old gpio driver and move new gpio2 support to the generic gpio driver folder. - To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's config header file. - The gpio2 driver supports bf54x, bf60x and future ADI processors, while the older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561. - All blackfin specific gpio function names are replaced by the generic gpio APIs. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| | * | blackfin: Move blackfin serial driver out of blackfin arch folder.Sonic Zhang2013-05-13-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move blackfin serial driver to the generic driver folder. - Move blackfin serial headers to blackfin arch head folder. - Update the include path to blackfin serial header in start up code. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| | * | blackfin: Move blackfin watchdog driver out of the blackfin arch folder.Sonic Zhang2013-05-13-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Enable hw_watchdog_init() in watchdog.h if CONFIG_HW_WATCHDOG is defined. - Move blackfin hw watchdog driver to the generic driver folder. - Call hw_watchdog_init() from blackfin board init code. - Reuse macro CONFIG_WATCHDOG_TIMEOUT_MSECS - Update README.watchdog accordingly Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| | * | blackfin: Enable early print via the generic serial API.Sonic Zhang2013-05-13-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove blackfin specific implementation of the generic serial API when early print macro is defined. In BFIN_BOOT_BYPASS mode, don't call generic serial_puts, because early print in bypass mode is running before code binary is relocated to the link address. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| | * | blackfin: Fit u-boot image size into limited nor flash on blackfin.Sonic Zhang2013-05-13-10/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Disable NAND driver on bf537-stamp. - Make MMC_SPI optional. - Disable LCD driver on bf527-ezkit. - Enlarge BF609 nor flash reserved size from 256k to 512k bytes. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
| | * | blackfin: bf609: add softswitch config commandBob Liu2013-05-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add softswitch_output command for bf609-ezkit to enable softswitches. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| | * | blackfin: run core1 from L1 code sram start address in uboot init code on core 0Sonic Zhang2013-05-13-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define core 1 L1 code sram start address. Add function to enable core 1 for BF609 and BF561. Add config macro to allow customer to run core 1 in uboot init code on core 0. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| | * | blackfin: reduce size of u-boot.ldr in bf548-ezkit default config.Bob Liu2013-05-13-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable VIDEO and NAND supports only when the config options is defined. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | | x86: config: Enable LZO for coreboot, remove zlib, gzipSimon Glass2013-05-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | We don't use zlib and gzip but do use lzo, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: Enable bootstage for corebootSimon Glass2013-05-13-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a convenient way of finding out where boottime is going. Enable it for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: Re-enable PCAT timer 2 for beepingSimon Glass2013-05-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | x86: Add TSC timerSimon Glass2013-05-13-3/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>
| * | gpio: Add support for microblaze xilinx GPIOMichal Simek2013-05-09-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microblaze uses gpio which is connected to the system reset. Currently gpio subsystem wasn't used for it. Add gpio driver and change Microblaze reset logic to be done via gpio subsystem. There are various configurations which Microblaze can have that's why gpio_alloc/gpio_alloc_dual(for dual channel) function has been introduced and gpio can be allocated dynamically. Adding several gpios IP is also possible and supported. For listing gpio configuration please use "gpio status" command This patch also remove one compilation warning: microblaze-generic.c: In function 'do_reset': microblaze-generic.c:38:47: warning: operation on '*1073741824u' may be undefined [-Wsequence-point] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL buildAxel Lin2013-05-28-0/+2
| | | | | | | | | | | | | | | | Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: Remove unused/non-existent spl linker script referenceTom Warren2013-05-28-6/+0
| | | | | | | | | | | | | | Tegra builds use the common u-boot-spl.lds now. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | ARM: Add Seagate GoFlex Home supportSuriyan Ramasami2013-05-23-0/+151
| | | | | | | | | | | | | | | | | | Add Seagate GoFlex Home support Start with dockstar configuration define support for RTC, DATE, SATA and EXT4FS Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
* | ARM: vexpress: enable bootz and hush parser for all VExpress boardsAndre Przywara2013-05-23-0/+4
| | | | | | | | Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | ARM: vexpress: add support for Versatile Express Cortex-A15-TC2Andre Przywara2013-05-23-0/+36
| | | | | | | | | | | | | | | | This adds support for the Cortex-A15-TC2 core tile for the Versatile Express board by ARM. This is mostly a copy of the A5 support file, but will be extended later with A15 specific options. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | ARM: vexpress: create A5 specific board configRyan Harkin2013-05-23-19/+167
| | | | | | | | | | | | | | | | | | | | | | | | This patch creates a new config for the A5 dual core tile that includes the generic config for the Versatile Express platform. The generic config has been modified to provide support for the Extended Memory Map, as used on the A5 core tile. A5 does not support the legacy memory map. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | ARM: vexpress: refactoring of Versatile Express CA9x4 supportRyan Harkin2013-05-23-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ca9x4_ct_vxp platform contains support for a Versatile Express motherboard with a quad core A9 core tile. This patch separates the Versatile Express motherboard code and the A9 specific code, to ease supporting more core tiles in the next patches. Andre: merged the first two of Ryan's original patches and did some checkpatch fixes. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
generated by cgit v1.1 at 2024-09-18 16:19:12 +0000