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* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-26-5/+50
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| * armv8/ls1043a: Add MTD partition schemeWenbin Song2016-07-26-2/+20
| | | | | | | | | | | | | | | | Add and share the the MTD partition scheme with kernel by default bootargs. And add the "mtdparts" env. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/ls1046a: Cleanup the environment variablesWenbin Song2016-07-26-4/+1
| | | | | | | | | | | | | | | | Cleanup the variables: "kernel_addr","ramdisk_addr", "ramdisk_size","console". Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: PSCI: ls102xa: move secure text section into OCRAMHongbo Zhang2016-07-26-0/+4
| | | | | | | | | | | | | | | | | | LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1021atwr: Add SD secure boot targetSumit Garg2016-07-26-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SD secure boot target for ls1021atwr. Implement board specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-07-26-0/+16
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| * | defconfig: am335x_boneblack_vboot: enable i2c driver modelMugunthan V N2016-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable i2c driver model for am335x_boneblack_vboot as omap i2c supports driver model. Also enable CONFIG_DM_I2C_COMPAT for legacy drivers of i2c devices. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | ti_armv7_common: i2c: do not define DM_I2C for splMugunthan V N2016-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Since omap's spl doesn't support DM currently, do not define DM_I2C for spl build. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM64: rockchip: add support for rk3399 SoC based evbKever Yang2016-07-25-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: rk3288: add fastboot supportXu Ziyuan2016-07-25-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable fastboot feature on rk3288. This path doesn't support the fastboot flash function command entirely. We will hit "cannot find partition" assertion without specified partition environment. Define gpt partition layout in specified board such as firefly-rk3288, then enjoy it! Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | rockchip: add basic support for evb-rk3288 boardXu Ziyuan2016-07-25-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | evb-3288 board RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to display pins, I2C, SPI, UART and GPIOs. This add some basic files required to allow the board to output serial messaged and can run command(mmc info etc). evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | rockchip: add option to change method of loading u-bootXu Ziyuan2016-07-25-0/+5
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: Migrate CONFIG_I2C_EEPROMTom Rini2016-07-25-1/+0
| | | | | | | | | | | | | | | | | | Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago, but sandbox was skipped. Leave it off for sandbox_spl where it does not build, but does not need to be either. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-07-25-0/+3
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| * | sunxi: nand: Increase CONFIG_SYS_NAND_MAX_ECCPOS valueBoris Brezillon2016-07-24-0/+1
| | | | | | | | | | | | | | | | | | | | | On some sunxi boards we have NANDs exposing 1664 OOB bytes per page. Define the CONFIG_SYS_NAND_MAX_ECCPOS value accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | mtd: nand: Add the sunxi NAND controller driverBoris Brezillon2016-07-24-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | We already have an SPL driver for the sunxi NAND controller, now add the normal/standard one. The source has been copied from Linux 4.6 with a few changes to make it work in u-boot. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | sandbox: Add instructions about building on 32-bit machinesSimon Glass2016-07-25-1/+4
|/ | | | | | | | Sandbox is built with 64-bit ints by default. This doesn't work properly on 32-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: fix doubled tftpboot commandsMasahiro Yamada2016-07-23-1/+0
| | | | | | This downloads the same file twice for nothing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* igep00x0: generate default mtdparts according NAND chip usedLadislav Michl2016-07-22-0/+1
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* igep00x0: UBIizeLadislav Michl2016-07-22-47/+38
| | | | | | | | | | | | Convert IGEP board to use UBI volumes for U-Boot, its environment and kernel. With exception of first four sectors read by SoC boot ROM whole (One)NAND is UBI managed. Also merge NAND and OneNAND defconfigs as now one binary can serve both flashes. As code is too big now, drop CONFIG_SPL_EXT_SUPPORT to make it fit. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-07-22-93/+2
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| * zynq: defconfig: Remove unnecessary board specific config filesSiva Durga Prasad Paladugu2016-07-22-60/+0
| | | | | | | | | | | | | | | | | | Remove unnecessary board specifc config files for zynq boards(microzed, picozed, ZC770(all), zed) and point to zynq common config file. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: config: Enable CONFIG_SYS_NO_FLASH through defconfigSiva Durga Prasad Paladugu2016-07-22-17/+0
| | | | | | | | | | | | | | | | Enable config CONFIG_SYS_NO_FLASH through defconfig for all zynq boards. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * usb: zynq: Define config USB_STORAGE through defconfigSiva Durga Prasad Paladugu2016-07-22-1/+0
| | | | | | | | | | | | | | | | Define config USB_STORAGE through defconfig for all respective zynq boards Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * usb: Kconfig: Add Kconfigs entry USB_EHCI_ZYNQSiva Durga Prasad Paladugu2016-07-22-11/+1
| | | | | | | | | | | | | | | | | | Add Kconfig entry config option for USB_EHCI_ZYNQ and update the same to enable for all zynq boards which supports USB Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Enable AHCI on EP platformAlexander Graf2016-07-22-0/+1
| | | | | | | | | | | | | | | | The EP platform also has working AHCI emulation, so I see little reason not to implement the plumbing for it that enables us to boot from AHCI. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Remove empty ifdef around cachesMichal Simek2016-07-22-4/+0
| | | | | | | | | | | | Code around was removed because of move to Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | powerpc/85xx: Increase fdt addressScott Wood2016-07-21-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading the fdt at 0xc00000 fails if the uncompressed kernel image is greater than 12 MiB, which is quite common with modern kernels and multiplatform defconfigs. Move fdtaddr to 0x1e00000 which is just under the ramdiskaddr on most targets. Signed-off-by: Scott Wood <oss@buserror.net> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Paul Gortmaker <paul.gortmaker@windriver.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mpc83xx: make it bootable with the latest kernelKevin Hao2016-07-21-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the blow up of the latest kernel size, the default gnuzip size (8M) seems too small. The yocto kernel size I built for mpc8315erdb board is 5294393, and it can't be boot by using the latest u-boot. So expand gnuzip buffer for all the mpc83xx boards to fix this issue. Robert P. J. Day also pointed that the kernel partition on the NAND flash is also too small, fix it at the same time. Reported-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Kevin Hao <kexin.hao@windriver.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mpc83xx: fix the corruption of u-boot when saveenvKevin Hao2016-07-21-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Robert P. J. Day has pointed that the value of SYS_MONITOR_LEN in MPC8315ERDB.h is smaller than the u-boot.bin. This will cause the overlap between the code of u-boot and the environment variable. So when executing saveenv, it will corrupt the code of u-boot and causes the board not boot. Fix this for all the mpc83xx boards by reserving a 512K area. Reported-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Kevin Hao <kexin.hao@windriver.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc: MPC8544DS: revert typo in I2C offset valueBenjamin Kamath2016-07-20-1/+1
|/ | | | | | | | | | I2C offset was changed by commit 00f792e0 (added multibus support) from 0x3100 to 0x3000. This typo leads to error when reading SPD from DDR DIMMs. Signed-off-by: Benjamin Kamath <bkamath@spaceflight.com> Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-0/+11
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * ARMv8/ls1043ardb: Integrate FSL PPAHou Zhiqiang2016-07-19-0/+11
| | | | | | | | | | | | | | | | | | The PPA use PSCI to make secondary cores bootup. So when PPA was enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method between PSCI and spin-table. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | configs: Add more CONFIG_ARMV7_PSCI_NR_CPUS entriesTom Rini2016-07-16-0/+3
| | | | | | | | | | | | | | | | | | | | | | The code had assumed 4 CPUS before and now we have this configurable. For now, set this to the previous default. Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-0/+11
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| * | sunxi: Define CONFIG_ARMV7_SECURE_MAX_SIZE for sun6i/sun7iChen-Yu Tsai2016-07-15-0/+2
| | | | | | | | | | | | | | | | | | | | | Both sun6i and sun7i have 64 KB of secure SRAM. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | ARM: PSCI: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for PSCI enabled platformsChen-Yu Tsai2016-07-15-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The original PSCI implementation assumed CONFIG_ARMV7_PSCI_NR_CPUS=4. Add this to platforms that have not defined it, using CONFIG_MAX_CPUS if it is defined, or the actual number of cores for the given platform. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add missing CONFIG_ARMV7_PSCI_NR_CPUS for sun7iChen-Yu Tsai2016-07-15-0/+1
| | | | | | | | | | | | | | | | | | | | | sun7i has 2 CPUs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-07-15-0/+24
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| * | sandbox: Add a test device that uses of-platdataSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Start up the test devices. These print out of-platdata contents, providing a check that the of-platdata feature is working correctly. The device-tree changes are made to sandbox.dts rather than test.dts. since the former controls the of-platdata generation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Add a new sandbox_spl boardSimon Glass2016-07-14-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to build SPL for sandbox. It provides additional build coverage and allows SPL features to be tested in sandbox. However it does not need worthwhile to always create an SPL build. It nearly doubles the build time and the feature is (so far) seldom used. So for now, create a separate build target for sandbox SPL. This allows experimentation with this new feature without impacting existing workflows. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Don't use IDE and iotrace in SPLSimon Glass2016-07-14-0/+4
| |/ | | | | | | | | | | These functions are not supported in SPL, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | stm32: Add SDRAM support for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-4/+4
| | | | | | | | | | | | | | | | | | | | This patch adds SDRAM support for stm32f746 discovery board. This patch depends on previous patch. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | stm32: clk: Add 200MHz clock configuration for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-1/+2
| | | | | | | | | | | | | | | | | | This patch adds 200MHz clock configuration for stm32f746 discovery board. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | dragonboard410c: adding missing default addr for script and pxe bootRicardo Salveti de Araujo2016-07-14-0/+2
| | | | | | | | | | Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Ricardo Salveti <rsalveti@rsalveti.net>
* | dragonboard410c: prefer sdcard boot over emmcRicardo Salveti de Araujo2016-07-14-1/+1
|/ | | | | | | | | | | | Make the external devices the preferred ones when booting the system (usb is already the first option). This allows users to easily boot custom distributions without requiring them to reflash/customize u-boot. Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Ricardo Salveti <rsalveti@rsalveti.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: Andreas Färber <afaerber@suse.de> Acked-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
generated by cgit v1.1 at 2024-09-15 07:26:23 +0000