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* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-10-17-56/+46
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| * i2c: update config using mxc driver to new subsystemtrem2013-10-17-56/+46
| | | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* | powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-paShengzhou Liu2013-10-16-14/+87
| | | | | | | | | | | | | | | | | | | | | | | | - Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization. For more details, see board/freescale/p1010rdb/README. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix conflicts in boards.cfg] Acked-by: York Sun <yorksun@freescale.com>
* | board/p1010rdb: add pin mux and sdhc support in any bootShengzhou Liu2013-10-16-13/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since pins multiplexing, SDHC shares signals with IFC, with this patch: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha2013-10-16-0/+761
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
* | powerpc/B4860: enable PBL tool for B4860Shaohui Xie2013-10-16-0/+2
| | | | | | | | | | | | | | | | Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* | powerpc/usb: Mention usb1 before usb2 inside default hwconfig stringramneek mehresh2013-10-16-2/+2
| | | | | | | | | | | | | | | | For USB device-tree fix-up to work properly, its necessary to mention USB1 options before that of USB2 inside default hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* | board/bsc9131rdb: Update IFC timings for NAND flashPrabhakar Kushwaha2013-10-16-8/+8
| | | | | | | | | | | | | | | | | | Current IFC timings for NAND flash are not able to support existing K9F1G08U0B and new K9F1G08U0D flash. so Update the timings to support both. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand bootYing Zhang2013-10-16-26/+57
| | | | | | | | | | | | Enable TPL for p1_p2_rdb_pc nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPLYing Zhang2013-10-16-7/+29
| | | | | | | | | | | | Enable p1_p2_rdb_pc to start from eSPI with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPLYing Zhang2013-10-16-14/+45
| | | | | | | | | | | | Enable p1_p2_rdb_pc to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
* | powerpc:c29xpcie: make ifc timing parameter flexiblePo Liu2013-10-16-3/+5
| | | | | | | | | | | | | | | | | | This patch re-config the NOR flash timing parameters which could make the ifc timing more flexible for NOR flash. The new parameters could fix the problem of hanging at "Flash:" occasionally when booting the board. Signed-off-by: Po Liu <Po.Liu@freescale.com>
* | powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.hPo Liu2013-10-16-10/+0
|/ | | | | | | This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
* Coding Style cleanup: drop some excessive empty linesWolfgang Denk2013-10-14-4/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-14-16/+16
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-262/+262
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* am335x_evm.h: Make 'am335x_boneblack' use redundant environmentTom Rini2013-10-14-0/+3
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-14-0/+311
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| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-10-11-0/+311
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| | * samsung: trats2: add support for new board Trats2Piotr Wilczek2013-09-25-0/+311
| | | | | | | | | | | | | | | | | | | | | | | | This patch add support for a new Samsung board Trats2. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | omap5_common: Re-work mmc boot to try SD and eMMC, correct root deviceTom Rini2013-10-09-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP5 boards may have both eMMC (on MMC2) and an SD slot (on MMC1). We Update the default bootcmd to match what happens on AM335x where we try SD first, and then eMMC. In this case however, the hardware layout used for powering both of these means that in the kernel eMMC shall be found first as it is powered by a fixed regulator and SD found second as SD is powered via the palmas which will result in deferred probing. Tested-by: Aparna Balasubramanian <aparnab@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | powerpc/km: drop unused CONFIG_SYS_DTT_LOW_TEMPHolger Brunck2013-10-09-2/+0
| | | | | | | | | | | | | | | | | | This define is not used in u-boot code, we can drop this define safely. Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* | | km/common: switch on CMD_GREPENVHolger Brunck2013-10-09-0/+1
| | | | | | | | | | | | Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* | | da850evm.h: Always set CONFIG_CMD_SF, move to by CONFIG_SPI_FLASHTom Rini2013-10-08-1/+1
| | | | | | | | | | | | | | | | | | When we have CONFIG_SPI_FLASH set we now require CONFIG_CMD_SF. Signed-off-by: Tom Rini <trini@ti.com>
* | | Revert "am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should ↵Tom Rini2013-10-08-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmcroot." Upon further inspection and review and chatting with kernel folks, what happens here is that what mmcblk# a device gets is based on probe order. So a system with an SD card inserted with place eMMC on mmcblk1, but without an SD card, it will be on mmcblk0. So U-boot can only provide a best guess. In this case, if no SD card is present, we would want to pass mmcblk0p2 still. If an SD card is present, it woudl be able to provide a uEnv.txt that would be loaded (even if the kernel is NOT there) which can still update mmcroot variable. This reverts commit 827512fb1154c05c6eb1e2259e936df55c98a535. Cc: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-08-177/+12
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| * | socfpga: Adding System Manager driverChin Liang See2013-10-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * | omap1510inn: arm925t: remove supportAlbert ARIBAUD2013-10-07-166/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | omap1510inn is orphan and has been for years now. Reove it and, as it was the only arm925t target, also remove arm925t support. Update doc/README.scrapyard accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | am335x_evm: Switch to zImage as default rather than uImageTom Rini2013-10-07-11/+11
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | | dra7xx_evm: add SPL API, QSPI, and serial flash supportMatt Porter2013-10-07-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | sf: ramtron: Add support for separate flash driverJagannadha Sutradharudu Teki2013-10-07-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Compared to other spi flashes, ramtron has a different probing and implementation on flash ops, hence moved ramtron probe code into ramtron driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-04-1/+4
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| * | ARM: VExpress: enable ARMv7 virt support for VExpress A15Andre Przywara2013-10-03-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable hypervisors utilizing the ARMv7 virtualization extension on the Versatile Express board with the A15 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the VExpress specific manner. There is no need to provide a custom smp_waitloop() function here. This also serves as an example for what to do when adding support for new boards. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * | ARM: add assembly routine to switch to non-secure stateAndre Przywara2013-10-03-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-02-6/+561
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| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-10-02-4/+546
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| | * | mx6sabresd: Fix the fdt file for the mx6dl versionFabio Estevam2013-09-20-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to load 'imx6dl-sabresd.dtb' in the mx6dl version. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * | mx6slevk: Add Ethernet supportFabio Estevam2013-09-20-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | mx35pdk: Remove CONFIG_SYS_CACHELINE_SIZEFabio Estevam2013-09-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In arch/arm/cpu/arm1136/cpu.c we have: #ifndef CONFIG_SYS_CACHELINE_SIZE #define CONFIG_SYS_CACHELINE_SIZE 32 #endif ,so there is no need to define 'CONFIG_SYS_CACHELINE_SIZE' with the default size in the board config file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | wandboard: Use imx6dl-wandboard.dtb for the solo versionFabio Estevam2013-09-20-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wandboard solo version should boot the 'imx6dl-wandboard.dtb' file, since dual-lite and solo variants are the same SoC with only the number of cores being different. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2013-09-13-3/+288
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: MAINTAINERS boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | | apf27: add FPGA support for the apf27 boardtrem2013-09-11-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | | apf27: add support for the armadeus APF27 boardtrem2013-09-11-0/+374
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org> Signed-off-by: Nicolas Colombain <nicolas.colombain@armadeus.com>
| | * | | ARM: mxs: Add SanDisk Sansa Fuze+ boardMarek Vasut2013-09-10-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add STMP3780-based Sansa Fuze+ board. This board is a small PMP device sporting a CPU which was later rebranded to i.MX233 . Currently supported is USB gadget mode and MMC . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * | | ARM: mxs: Add Creative ZEN XFi3 boardMarek Vasut2013-09-10-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add STMP3780-based XFi3 board. This board is a small PMP device sporting a CPU which was later rebranded to i.MX233 . Currently supported is USB gadget mode and both external SD and internal Phison SD-NAND bridge . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * | | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-10-02-1/+14
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| | * | | am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should mmcroot.Robert P. J. Day2013-09-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If, in CONFIG_BOOTCOMMAND, the environment switches both the mmcdev and bootpart variables to refer to MMC device 1, it would make sense that the mmcroot env variable should switch to that device as well. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
| | * | | ARM: DRA7: Enable saveenv commandLokesh Vutla2013-09-20-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dra7xx_evm has eMMC and the default environment can be stored in it. So enabling saveenv command and the configs to store environment in eMMC. Tested on DRA752 ES1.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * | | am335x:Handle worst case scenario for Errata 1.0.24Steve Kipisz2013-09-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Adapt to current framework] Signed-off-by: Tom Rini <trini@ti.com>
| | * | | am335x_evm: am33xx_spl_board_init function and scale core frequencyTom Rini2013-09-20-0/+5
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: Tom Rini <trini@ti.com>
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