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* dm: tegra: spi: Convert to driver modelSimon Glass2014-10-22-1/+3
| | | | | | | | | | | | | | This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: config: Use driver model for SPI flashSimon Glass2014-10-22-0/+1
| | | | | | | Use driver model for exynos5 board SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: sf: sandbox: Convert SPI flash driver to driver modelSimon Glass2014-10-22-0/+1
| | | | | | | Convert sandbox's spi flash emulation driver to use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* exynos: universal_c210: Move to driver model soft_spiSimon Glass2014-10-22-10/+1
| | | | | | | Adjust this board to use the driver model soft_spi implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: exynos: Convert SPI to driver modelSimon Glass2014-10-22-0/+1
| | | | | | | | | | Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: spi: Remove SPI_INIT featureSimon Glass2014-10-22-3/+0
| | | | | | | | | | | | This feature provides for init of a single SPI port for the soft SPI feature. It is not really compatible with driver model since it assumes a single SPI port. Also, inserting SPI init into the driver by means of a #define is not very nice. This feature is not used by any active boards, so let's remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: sandbox: spi: Move to driver modelSimon Glass2014-10-22-2/+1
| | | | | | | | Adjust the sandbox SPI driver to support driver model and move sandbox over to driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* dm: exynos: Move serial to driver modelSimon Glass2014-10-22-0/+3
| | | | | | | Change the Exynos serial driver to work with driver model and switch over all relevant boards to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: gpio: Convert to driver modelSimon Glass2014-10-22-0/+10
| | | | | | | Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Move s5p_goni to generic boardSimon Glass2014-10-22-0/+2
| | | | | | | The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for s5p_goni. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Move smdkc100 to generic boardSimon Glass2014-10-22-0/+2
| | | | | | | The generic board deadline is approaching, and we need this feature to enable driver model. Enable CONFIG_SYS_GENERIC_BOARD for smdkc100. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: goni: add i2c_init_board()Robert Baldyga2014-10-22-0/+2
| | | | | | | Add proper initialization of GPIO pins used by software i2c. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-10-20-1/+144
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| * ls102x: Add support for secure boot and enable blob commandRuchika Gupta2014-10-16-0/+8
| | | | | | | | | | Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Enable blob command in freescale platformsRuchika Gupta2014-10-16-0/+29
| | | | | | | | | | | | | | | | Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102x: configs - Add hash command in freescale LS1 platformsRuchika Gupta2014-10-16-0/+15
| | | | | | | | | | | | | | | | | | Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: configs - Add hash command in freescale platformsRuchika Gupta2014-10-16-0/+91
| | | | | | | | | | | | | | | | | | Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/P1010RDB:Update RESET_VECTOR_ADDRESS for 768KB u-boot sizeRuchika Gupta2014-10-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_RESET_VECTOR_ADDRESS to reflect the same for P1010 SPI Flash Secure boot target. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Modified subject to P1010RDB] Reviewed-by: York Sun <yorksun@freescale.com>
* | lcd: Fix build error with CONFIG_LCD_BMP_RLE8Simon Glass2014-10-16-0/+1
|/ | | | | | | | Add a block to avoid a build error with the variable declaration. Enable the option on sandbox to prevent an error being introduced in future. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot-socfpga/topic/arm/socfpga-20141010' into ↵Albert ARIBAUD2014-10-11-1/+1
|\ | | | | | | 'u-boot-arm/master'
| * arm: socfpga: Use EMAC1 on SoCDKMarek Vasut2014-10-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SoCDK uses EMAC1, not EMAC0. This patch fixes the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-2946/+273
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| * am335x_evm: Correct BOOTCOUNT driver supportTom Rini2014-10-10-0/+1
| | | | | | | | | | | | We need to set the 'BE' flag here for things to work right. Signed-off-by: Tom Rini <trini@ti.com>
| * VCMA9: remove EXT2 supportDavid Müller (ELSOFT AG)2014-10-10-1/+0
| | | | | | | | | | | | | | remove the seldomly used EXT2 support because the U-Boot binary will not fit into the 512KiB flash otherwise. Signed-off-by: David Müller <d.mueller@elsoft.ch>
| * PATI: fix broken SPI accessDavid Müller (ELSOFT AG)2014-10-10-0/+1
| | | | | | | | | | | | | | fix broken SPI access by adding/activating BOARD_EARLY_INIT_F functionality and calling spi_init_f() from there. Signed-off-by: David Müller <d.mueller@elsoft.ch>
| * PATI: convert to generic boardDavid Müller (ELSOFT AG)2014-10-10-0/+2
| | | | | | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
| * VCMA9: convert to generic boardDavid Müller (ELSOFT AG)2014-10-10-0/+2
| | | | | | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
| * MIP405: convert to generic boardDavid Müller (ELSOFT AG)2014-10-10-0/+2
| | | | | | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
| * PIP405: convert to generic boardDavid Müller (ELSOFT AG)2014-10-10-0/+2
| | | | | | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
| * powerpc: mpc5xxx: remove board support for MVBC_P and MVSMRMasahiro Yamada2014-10-10-570/+0
| | | | | | | | | | | | These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7Masahiro Yamada2014-10-10-1090/+0
| | | | | | | | | | | | These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: ppc4xx: remove board support for bluestoneMasahiro Yamada2014-10-10-168/+0
| | | | | | | | | | | | | | | | | | This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: ppc4xx: remove board support for CRAYL1Masahiro Yamada2014-10-10-228/+0
| | | | | | | | | | | | This board has been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: ppc4xx: remove board support for KAREF and METROBOXMasahiro Yamada2014-10-10-633/+0
| | | | | | | | | | | | These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * OMAP5+: sata/scsi: Implement scsi_init()Roger Quadros2014-10-10-1/+0
| | | | | | | | | | | | | | | | | | | | On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros <rogerq@ti.com>
| * omap3: overo: Fix fdtfile testStefan Herbrechtsmeier2014-10-10-1/+1
| | | | | | | | | | | | | | | | | | Commit 12cc54376768461533b55ada1b0b6d4979f40579 'omap3: overo: Select fdtfile for expansion board' wrongly missed the operator in the fdtfile test. Update the test to only overwrite an empty fdtfile environment variable. Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-10-07-6/+491
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| * \ Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-10-06-1/+1
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| | * | arm: am335x: siemens board use in DFU mode fullspeed onlyHeiko Schocher2014-10-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Siemens boards are now using DFU in fullspeed only. For this CONFIG_USB_GADGET_DUALSPEED is undefined. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Liu Bin <b-liu@ti.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com>
| * | | arm: socfpga: Use CMD_FS_GENERICMarek Vasut2014-10-06-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the filesystem type into the environment. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Split SoCFPGA configurationPavel Machek2014-10-06-200/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Clean up SoCFPGA configurationMarek Vasut2014-10-06-218/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize and cleanup the configuration file for SoCFPGA. There is no functional change after this cleanup. This was necessary, since the file was a wild mess and it was impossible to make sense of it's content, let alone change something without breaking some other thing. This patch puts the contents on par with regular U-Boot standards. Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER and CONFIG_USE_IRQ, which is undefined by default. Finally, do logical reordering of the defines in the file so it's much more readable. The reordering was also necessary for the splitting as the initial one was messy. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Enable SDMMC boot for SOCFPGA U-BootChin Liang See2014-10-06-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit. Enable the bootz command as zImage is used instead uImage. Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Enable DWMMC for SOCFPGAChin Liang See2014-10-06-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DesignWare MMC controller driver support for SOCFPGA Cyclone5 dev kit Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: cache: Enable PL310 L2 cacheMarek Vasut2014-10-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: cache: Enable D-CacheMarek Vasut2014-10-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code is now fixed to the point where we can safely enable the L1 data cache. Enable the D-Cache and set it as write-alloc. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: cache: Define cacheline sizeMarek Vasut2014-10-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cortex-A9 has 32-byte long L1 cachelines. Define this value. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: timer: Pull the timer reload value from config fileMarek Vasut2014-10-06-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: clock: Add code to read clock configurationPavel Machek2014-10-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)
| * | | net: Remove unused CONFIG_DW_SEARCH_PHY from configsPavel Machek2014-10-06-2/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove this symbol from configs, since it's unused. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Chin Liang See <clsee@altera.com>
generated by cgit v1.1 at 2024-09-19 20:02:21 +0000