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* Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-12-10-0/+11
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| * sandbox: spi: Enable new spi/sf layersMike Frysinger2013-12-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | We want to test SPI flash code in the sandbox, so enable the new drivers and the 'sf test' command. This command is used to validate the sandbox SPI / SPI flash implementation, so enable it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT nodeSimon Glass2013-12-09-0/+1
| | | | | | | | | | | | | | This allows us to put the SPI flash chip inside the SPI interface node, with U-Boot finding the correct bus and chip select automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-12-10-47/+32
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| * | driver:i2c:s3c24x0: adapt driver to new i2cPiotr Wilczek2013-12-05-47/+32
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adapts the s3c24x0 driver to the new i2c framework. Config file is modified for all the boards that use the driver. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Heiko Schocher <hs@denx.de> CC: Inderpal Singh <inderpal.singh@linaro.org> CC: David Müller <d.mueller@elsoft.ch> CC: Chander Kashyap <k.chander@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2013-12-06-27/+10
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| * | blackfin: soft-i2c: No need to define blackfin specific soft i2c operationsSonic Zhang2013-12-06-27/+2
| | | | | | | | | | | | | | | | | | | | | Use default GPIO operations. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | blackfin: Add missing macro CONFIG_BFIN_SERIALSonic Zhang2013-12-06-0/+6
| | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | blackfin: Use ADI_GPIO2 driver other than the default ADI_GPIO1Sonic Zhang2013-12-06-0/+2
| |/ | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | powerpc/mpc8349: Use generic mpc85xx DDR driverYork Sun2013-12-04-0/+1
| | | | | | | | | | | | | | | | | | | | MPC8349 has been using mpc85xx DDR driver through a symbolic link to mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set under driver/ddr/fsl/, the link is replaced by referring driver directly. We now can simply enable the macro and use the driver. Other mpc83xx SoCs still use their own driver. Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/t2080qds: undef CONFIG_FSL_DDR_INTERACTIVEShengzhou Liu2013-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Usually CONFIG_FSL_DDR_INTERACTIVE feature is used for debug. we would not enable this by default to save the limited space of u-boot. This avoid following compiling error: section .bootpg loaded at [00000000effff000,00000000effff577] overlap ssection .data loaded at [00000000efff31b8,00000000f00010c7] u-boot: section .bootpg lma 0xeffff000 adjusted to 0xf00010c8 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | powerpc/p1010rdb:modify the mtest start_addressZhao Qiang2013-12-04-1/+1
|/ | | | | | | | | In new board P1010RDB-PB, the interrupt vector table is at the start of memory. So if the start_address needs to be set a proper value. Signed-off-by: Zhao Qiang <B45475@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-12-02-1/+2
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| * malta: set CONFIG_SYS_BOOTM_LEN to 64MBPaul Burton2013-11-26-0/+1
| | | | | | | | | | | | | | Allow a larger kernel binary to be decompressed - the default 8MB can become limiting on a Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: correct UART baudratePaul Burton2013-11-26-1/+1
| | | | | | | | | | | | | | | | | | | | CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in a UART at 115200 baud, thus the x16 clock rate is 115200 * 16. Previously the divider was left at 0 which led to a rate of 38400 baud regardless of CONFIG_BAUDRATE or the baudrate environment variable. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-12-02-46/+864
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| * t2080qds/ramboot: enable PBL tool for t2080qdsShengzhou Liu2013-11-25-0/+2
| | | | | | | | | | | | | | | | Add the default RCW(SerDes 0x66_0x16) and PBI configure file for T2080QDS board, so we can use PBL tool to generate the ramboot image to support boot from NAND/SPI/SD. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * powerpc/t2080qds: add support for t2080qds boardShengzhou Liu2013-11-25-0/+803
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The T2080QDS is a high-performance computing evaluation, development and test platform supporting the T2080 QorIQ Power Architecture processor. T2080QDS feature overview Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz Memory: - Single memory controller capable of supporting DDR3 and DDR3-LV devices - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - Four 10Gbps XFI on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) PCIE: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) SATA: - Two SATA 2.0 ports on-board SRIO: - Two Serial RapidIO 2.0 ports up to 5 GHz eSDHC: - Supports SD/SDHC/SDXC/eMMC Card I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: removed Makefile blank line at EOF, fix conflicts with moving DDR driver] Acked-by: York Sun <yorksun@freescale.com>
| * Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-46/+46
| | | | | | | | | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
| * p1010rdb: enable mtdparts for NANDZhao Qiang2013-11-25-0/+7
| | | | | | | | | | | | | | | | The default partition table matches the .dts files for these boards in Linux. This allows these partitions to be used by name with U-Boot's "nand" command. Signed-off-by: Zhao Qiang <B45475@freescale.com>
| * powerpc/p4080: enable support for PCIe SATAShaohui Xie2013-11-22-0/+6
| | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | Merge branch 'sandbox1' of http://git.denx.de/u-boot-x86Tom Rini2013-11-25-1/+0
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| * | sandbox: config: Don't use 64-bit physical memorySimon Glass2013-11-21-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | Sandbox uses an emulated memory map which is quite small. We don't need the CONFIG_PHYS_64BIT option since we can address memory with a 32-bit offset into our ram_buf. Adjust the phys_addr_t and phys_size_t types accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-11-25-8/+35
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| * | mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-schemepekon gupta2013-11-21-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed CONFIG_xx used for selecting NAND ecc-schemes. This patch aims at solving following issues. 1) Currently ecc-scheme is tied to SoC platform, which prevents user to select other ecc-schemes also supported in hardware. like; - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW). - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware supports BCH16 ecc-scheme also. 2) Different platforms use different CONFIG_xx to select ecc-schemes, which adds confusion for user while migrating platforms. - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only 8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW) whereas ELM hardware engine supports other ecc-schemes also like; BCH4, and BCH16 (in future). - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW). - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency on SoC platform and NAND driver. And user can select ecc-scheme independently foreach board. However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand) Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx ↵pekon gupta2013-11-21-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platforms ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include <asm/elm.h> - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform. Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | board/c29xpcie: Add support of 8K page size NAND flashPrabhakar Kushwaha2013-11-21-4/+6
| | | | | | | | | | | | | | | | | | Defines constants required to support 8K page size NAND flash. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * | mtd: move & update nand_ecclayout structure (plus board changes)Prabhakar Kushwaha2013-11-21-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Changes from Prabhabkar's version (squashed into one patch to preserve bisectability): - Added _LARGE to MTD_MAX_*_ENTRIES This makes the names match current Linux source, and resolves a conflict between http://patchwork.ozlabs.org/patch/280488/ and http://patchwork.ozlabs.org/patch/284513/ The former was posted first and is closer to matching Linux, but unlike Linux it does not add _LARGE to the names. The second adds _LARGE to one of the names, and depends on it in a subsequent patch (http://patchwork.ozlabs.org/patch/284512/). - Made max oobfree/eccpos configurable, and used this on tricorder, alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build for me without doing so, due to a size increase). On tricorder SPL, this saves 2576 bytes (and makes the SPL build again) versus the new default of 640 eccpos and 32 oobfree, and saves 336 bytes versus the old default of 128 eccpos and 8 oobfree. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Vipin Kumar <vipin.kumar@st.com> [scottwood@freescale.com: changes as described above] Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Thomas Weber <weber@corscience.de> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Cc: Stefan Roese <sr@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | | spieval: Remove remainders of dead boardMasahiro Yamada2013-11-25-494/+0
| |/ |/| | | | | | | | | | | Commit 69434e4c deleted spieval board support but it missed to clean up include/configs/spieval.h file. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-11-17-2/+2
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| * | malta: use unmapped flash base addressGabor Juhos2013-11-15-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The physical base address of the NOR flash is 0x1e000000 on the Malta boards. The hardware also maps the first 4MiB of the flash into the 0x1fc00000-0x1fffffff range. Currently, U-Boot uses the mapped address to access the flash, which does not work in recent qemu versions. Since commit a427338b222b43197c2776cbc996936df0302f51 (mips_malta: correct reading MIPS revision at 0x1fc00010) writing to the mapped address space causes a CPU exception. Due to the exception, U-Boot hangs during boot when it tries to detect the CFI flash chip. Use the correct physical address for the MALTA_FLASH_BASE constant to fix the problem. In order to avoid relocation problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE constants. The change makes it possible to start U-Boot on a Malta board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also works on older versions (tested with 1.1.1, 1.2.2, 1.4.2, 1.5.3). Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* | Makefile: rename all libraries to built-in.oMasahiro Yamada2013-11-17-20/+20
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | configs: clean up unused macro CONFIG_L2_OFFMasahiro Yamada2013-11-15-11/+0
| | | | | | | | | | | | | | | | Since commit c2dd0d455 and 45bf05854 introduced the new cache maintainance framework to ARM, CONFIG_L2_OFF has not been used at all. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-11-14-0/+1386
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| * | powerpc/t104xrdb: Add T1042RDB_PI board supportPriyanka Jain2013-11-13-0/+694
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Two on-board RGMII 10/100/1G ethernet ports. - SERDES Connections, 8 lanes supporting: — PCI — SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Video - DIU supports video at up to 1280x1024x32bpp - HDMI connector - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| * | powerpc/t104xrdb: Add T1040RDB board supportPriyanka Jain2013-11-13-0/+690
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040RDB is Freescale Reference Design Board supporting the T1040 QorIQ Power Architecture™ processor. T1040RDB board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefile] Acked-by: York Sun <yorksun@freescale.com>
| * | powerpc/t1040: enable PBL tool for T1040Prabhakar Kushwaha2013-11-13-0/+2
| |/ | | | | | | | | | | | | | | Use a default RCW of protocol 0x66. A PBI configure file which uses CPC as 256KB SRAM. It can be used by PBL tool on T1040 to build a pbl boot image. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | i2c, zynq: convert zynq i2c driver to new multibus/multiadapter frameworkHeiko Schocher2013-11-13-4/+4
| | | | | | | | | | | | | | | | | | - add zync i2c driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com>
* | i2c, omap24xx: convert driver to new mutlibus/mutliadapter frameworkHeiko Schocher2013-11-13-101/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Tom Rini <trini@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Thomas Weber <weber@corscience.de> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Luca Ceresoli <luca.ceresoli@comelit.it> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Nishanth Menon <nm@ti.com> Cc: Pali Rohár <pali.rohar@gmail.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Michael Jones <michael.jones@matrix-vision.de> Cc: Raphael Assenat <raph@8d.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Stefano Babic <sbabic@denx.de>
* | i2c: sh_i2c: Update to new CONFIG_SYS_I2C frameworkNobuhiro Iwamatsu2013-11-13-23/+23
|/ | | | | | | | This updates to new I2C framwwork on sh_i2c. And this also updates boards(kzm9g and ecovec) that using sh_i2c. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* cm_t35: use scf0403 driverNikita Kiryanov2013-11-12-0/+3
| | | | | | | | Use scf0403 driver to add scf0403x LCD support for cm-t35 and cm-t3730 boards. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* MPC824x: remove obsolete "PN62" boardWolfgang Denk2013-11-11-285/+0
| | | | | | | | | | | The MPC824x processors have long reached EOL, and the PN62 board has not seen any board-specific updates for more than a decade. It is now causing build issues. Instead of wasting time on things nobody is interested in any more, we rather drop this board. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@grandegger.com> cc: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-11-11-17/+28
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| * malta: define CONFIG_MEMSIZE_IN_BYTESGabor Juhos2013-11-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The memsize environment variable must contain the memory size in bytes on the Malta board. Otherwise Linux will use wrong memory size which causes a kernel panic. Define CONFIG_MEMSIZE_IN_BYTES in malta.h to avoid that. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * malta: store environment in flashPaul Burton2013-11-09-6/+9
| | | | | | | | | | | | | | | | | | Allow the environment to be stored in the monitor flash of a Malta board. The environment is stored in the final 128KB of the flash, which both leaves the majority of the flash available for U-boot code and also matches the location which YAMON uses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: enable RTC supportPaul Burton2013-11-09-0/+5
| | | | | | | | | | | | | | | | | | This is actually required in order for a Linux kernel to boot successfully on a physical Malta board. Without enabling the RTC, a Malta Linux kernel will get stuck in its estimate_frequencies function on boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: remove cache size definitionsPaul Burton2013-11-09-4/+0
| | | | | | | | | | | | | | | | | | | | These will now be detected at runtime, allowing a single U-boot configuration to function correctly with different bitstreams. Without this you may need to re-configure, re-build and re-flash U-boot to your Malta if you flash a new bitstream with a different cache configuration to your old bitstream. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: enable CONFIG_PCNET_79C973, PCNET_HAS_PROM, CONFIG_CMD_DHCPPaul Burton2013-11-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This model of the pcnet is used in current Malta boards, at least in the Malta-R rev 3. Enable support for it. The Malta also has the ethernet controller PROM containing its MAC address, so enable support for that in order to read that MAC address. DHCP is a very useful feature to have available for many networks, enable support for it also. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: support for coreFPGA6 boardsPaul Burton2013-11-09-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * qemu-malta: rename to just "malta"Paul Burton2013-11-09-6/+6
| | | | | | | | | | | | | | | | | | This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
generated by cgit v1.1 at 2024-07-17 07:33:39 +0000