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| * | | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2014-12-30-6/+68
| |\ \ \ \ | | | |/ / | | |/| | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | | ot1200: enable support for USB_STORAGEChristian Gmeiner2014-12-19-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | | | ot1200: add fsuuid commandChristian Gmeiner2014-12-19-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | | | imx:mx6qarm2 add board level support for usbPeng Fan2014-12-19-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings and implement board_ehci_hcd_init Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | | imx:mx6sabresd add board level support for usbPeng Fan2014-12-19-0/+14
| | |/ / | |/| | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2014-12-30-29/+92
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| * | | Exynos: Move down common USB configurationSjoerd Simons2014-12-30-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB is a pretty common feature on exynos 5 board, so it seems sensible to configure it directly from exynos5-common. As a side-effect this makes USB available from u-boot on exynos 5420 based boards. While there enable support for common USB ethernet cards to make it more likely the default config allows booting for network and enable XHCI on SMDK5420 which has it defined in the dts but not in its config. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | odroid-XU3: Add entry for DTS EHCI GPIOSjoerd Simons2014-12-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add samsung,vbus-gpio information for the XU3. This allows the usage of the EHCI controller on the XU3, which is connected to the SMSC LAN9514 chip (usb hub + network). Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang2014-12-22-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | config: exynos5420: move non common configs to specific board filesHyungwon Hwang2014-12-22-18/+23
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The media for boot and environment is a board-specific feature, not a processor-specific. This is same to console port number and some other addresses. This patch moves the that kinds of configs to each board-specific files from the common config file for Exynos5420. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | vexpress64: switch to generic boardLinus Walleij2014-12-29-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The few Versatile Express ARMv8 platforms we have may just as well be switched to generic board from the beginning. Tested on the ARM foundation model and the in progress support for the ARMv8 Juno board. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Steve Rae <srae@broadcom.com>
* | | x86: Rename coreboot-serial to x86-serialBin Meng2014-12-18-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: crownbay: Add SDHCI supportBin Meng2014-12-18-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: crownbay: Enable Intel E1000 NIC supportBin Meng2014-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: crownbay: Add SPI flash supportBin Meng2014-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Include FSP and CMC binary in the u-boot.rom build rulesBin Meng2014-12-18-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Add crownbay defconfig and config.hBin Meng2014-12-18-0/+52
|/ / | | | | | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: UniPhier: enable CONFIG_CMD_DMMasahiro Yamada2014-12-18-0/+2
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: use DRAM area for init stack of normal imageMasahiro Yamada2014-12-18-0/+4
|/ | | | | | | The normal image is working on DRAM. It is better to use DRAM also for init stack than L2 cache. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-12-16-8/+245
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| * mpc85xx/t104xrdb: convert deep sleep to generic board interfaceTang Yuantian2014-12-15-0/+3
| | | | | | | | | | | | | | | | A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/T10xx: Fix number of portalsJeffrey Ladouceur2014-12-15-8/+8
| | | | | | | | | | | | | | | | | | | | | | Following boards has incorrect number of portals defined. powerpc/T102xQDS powerpc/T102xRDB powerpc/T1040QDS powerpc/T104xRDB Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur2014-12-15-0/+224
| | | | | | | | | | | | | | | | | | Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/p2041rdb: enable generic board configsShaohui Xie2014-12-15-0/+2
| | | | | | | | | | | | | | | | | | Add following configs in header file: CONFIG_SYS_GENERIC_BOARD CONFIG_DISPLAY_BOARDINFO Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t4240rdb: Convert to use generic board codeChunhe Lan2014-12-15-0/+2
| | | | | | | | | | Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/bsc913x: Convert to use generic board codeharninder rai2014-12-15-0/+6
| | | | | | | | | | Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-1/+32
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| * | arm: socfpga: DW_SPI: Remove clock info from config headerStefan Roese2014-12-06-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the now unnecessary clocking info from the SoCFPGA config header. As this info in now used directly in the SPI driver itself. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Add Designware (DW) SPI support to config headerStefan Roese2014-12-06-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Add Cadence QSPI support to config headerStefan Roese2014-12-06-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this driver enabled for SoCFPGA, access to SPI NOR flash is supported. The configuration (page size, timing info) will be taken from the DT. See socrates as an example. This QSPI supports depends on DT. So QSPI is only enabled if CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-58/+84
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| * | dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-60/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | ARM: tegra: Add support for nyan-big boardAllen Martin2014-12-11-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here. The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> (rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
| * | dm: i2c: config: Enable I2C for sandbox using driver modelSimon Glass2014-12-11-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Enable the options to bring up I2C on sandbox. Also enable all the available I2C commands for testing purposes. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * | dm: rpi: Move serial to driver modelSimon Glass2014-12-11-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Adjust the configuration to use the driver model version of the pl01x serial driver. Add the required platform data. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-0/+28
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | imx:mx6sxsabresd add board level support for usbPeng Fan2014-11-14-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6sxsabresd board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to make host port work in HOST mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
| * | | imx:mx6slevk add board level support for usbPeng Fan2014-11-14-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-2/+269
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| * | | ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7iXiubo Li2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ. It should be CONFIG_TIMER_CLK_FREQ. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> [York Sun: This is the difference between two patch versions] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls102xa: changing a few targets' configurations.Xiubo Li2014-12-11-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li2014-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang2014-12-11-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE supportAlison Wang2014-12-11-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SD/NAND/QSPI boot definations are wrong for QE support, this patch is to fix this error. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT supportAlison Wang2014-12-11-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will fix the bug that the partitions on the SD card could not be accessed and add the support for the FAT fs. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add SD boot support for LS1021ATWR boardAlison Wang2014-12-11-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-08-23 08:41:42 +0000