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path: root/include/configs/yucca.h
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* Replace "run load; run update" with conditionalized "run load update".Detlev Zundel2008-03-06-2/+2
| | | | | | | The latter version stops when "run load" fails for whatever reasons rendering the combination *a lot* more secure. Signed-off-by: Detlev Zundel <dzu@denx.de>
* Fix quoting problem (preboot setting) in many board config files.Wolfgang Denk2008-03-03-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Remove cache definition from 4xx board config filesStefan Roese2007-10-31-8/+0
| | | | | | | All 4xx board config files don't need the cache definitions anymore. These are now defined in common headers. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support addedStefan Roese2007-10-31-0/+3
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & KatmaiStefan Roese2007-10-31-1/+1
| | | | | | | | | | | | | | | | | 128MB seems to be the smallest possible value for the memory size for on PCIe port. With this change now the BAR's of the PCIe cards are accessible under U-Boot. One big note: This only works for PCIe port 0 & 1. For port 2 this currently doesn't work, since the base address is now 0xc0000000 (0xb0000000 + 2 * 0x08000000), and this is already occupied by CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean to change the base addresses completely and this change would have too much impact right now. This patch adds debug output to the 4xx pcie driver too. Signed-off-by: Stefan Roese <sr@denx.de>
* [PPC440SPe] PCIe environment settings for Katmai and YuccaGrzegorz Bernacki2007-09-07-1/+2
| | | | | | | | | | | | - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* [PPC440SPe] Improve PCIe configuration space accessGrzegorz Bernacki2007-09-07-5/+5
| | | | | | | | | | | | | - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* lib_ppc: make board_add_ram_info weakKim Phillips2007-08-18-1/+0
| | | | | | | | | | | | platforms wishing to display RAM diagnostics in addition to size, can do so, on one line, in their own board_add_ram_info() implementation. this consequently eliminates CONFIG_ADD_RAM_INFO. Thanks to Stefan for the hint. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*.Jon Loeliger2007-07-10-0/+9
| | | | | | | | | Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* include/configs: Use new CONFIG_CMD_* in various [v-z]* named board config ↵Jon Loeliger2007-07-05-22/+25
| | | | | | files. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-1/+0
| | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change Yucca config file to support ECCStefan Roese2007-03-31-1/+1
| | | | | | | With the updated 44x DDR2 driver the Yucca board now supports ECC generation and checking. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update AMCC Yucca 440SPe eval board supportStefan Roese2007-03-08-7/+7
| | | | | | | | | The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update some AMCC 4xx board config files (set initrd_high)Stefan Roese2007-02-07-0/+1
| | | | | | | | Some boards that can have more than 768MBytes of SDRAM need to set "initrd_high", so that the initrd can be accessed by the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
* Cleanup debug code for yucca board.Wolfgang Denk2006-08-17-3/+0
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* Merge with /home/sr/git/u-boot/denxWolfgang Denk2006-08-13-0/+9
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| * Add commandline history support to all AMCC eval boardsStefan Roese2006-08-07-0/+9
| | | | | | | | Patch by Stefan Roese, 07 Aug 2006
* | Fix PCI-Express on PPC440SPe rev. A.Rafal Jaworowski2006-08-11-8/+2
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* | Add support for PCI-Express on PPC440SPe (Yucca board).Rafal Jaworowski2006-08-10-11/+21
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* Fix timer problems on AMCC yucca board.Marian Balakowicz2006-07-06-1/+1
| | | | Set Timer Clock Select to use CPU clock as a timer input source.
* Bring yucca config more in line with other AMCC boards.Wolfgang Denk2006-07-05-29/+33
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* Add system memory to the PCI region list for AMCC PPC44x CPUs.Marian Balakowicz2006-07-04-0/+5
| | | | Enabled it for Yucca board.
* Cleanup config file and bootup output for Yucca board.Marian Balakowicz2006-07-03-5/+4
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* Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz2006-06-30-0/+518
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