| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
| |
Fix the timeout issue after running "bootp" command in u-boot
console. For example you see "EHCI timed out on TD- token=0x...".
TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10
after a controller reset and before RUN bit is set
(per technical reference manual).
Signed-off-by: Jim Lin <jilin@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
|
|
|
|
|
|
|
|
| |
Add USB EHCI, storage and network support.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
| |
|
|
|
|
|
| |
Tegra builds use the common u-boot-spl.lds now.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
|
| |
|
|
|
|
|
|
| |
Tested all 5 'buses', i2c probe enumerates device addresses on bus
0, 1 and 2.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
|
This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
