arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
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*	powerpc/t4240qds: Add voltage ID support	York Sun	2013-05-14	-2/+10
\| \| \| \| \| \| \| \|	T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	powerpc/t4240qds: fix XAUI card PHY address	Shaohui Xie	2013-05-14	-4/+4
\| \| \| \| \| \|	Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	powerpc/t4240qds: Fix SPI flash type	Shaohui Xie	2013-05-14	-1/+1
\| \| \| \| \| \| \|	T4240QDS uses a SST instead of SPANSION SPI flash. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	powerpc/t4240qds: Update IFC timing for NOR flash	York Sun	2013-01-30	-5/+5
\| \| \| \| \| \| \| \|	Relax parameters to give address latching more time to setup. Tighten parameters to make it overall faster. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	boards/T4240qds:Fix IFC AMASK init as per FPGA register space	Prabhakar Kushwaha	2013-01-30	-1/+1
\| \| \| \| \| \| \| \| \| \|	T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's Address Mask Registers is initialised 64K size. So Fix the Address Mask Register initilisation as 4K Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	powerpc/t4qds: Add T4QDS board	York Sun	2012-10-22	-0/+875
	The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>