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path: root/include/configs/socfpga_common.h
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* arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD usefulMarek Vasut2015-08-08-0/+4
| | | | | | | | Enable the mtdparts command and related options to make support for SPI NOR MTD useful in any way. With the mtdparts command in place, it is possible to use partition of the SPI NOR in U-Boot. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Enable CONFIG_SPI_FLASH_BARMarek Vasut2015-08-08-0/+1
| | | | | | | This is needed to access broken (read: Micron) SPI flashes which are larger than 16 MiB and don't correctly support 4-byte addressing. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL buildMarek Vasut2015-08-08-0/+2
| | | | | | | We do not need full MTD support in the SPL build, it only adds size and is not usable in any way. Exclude it. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Zap incorrect config optionsMarek Vasut2015-08-08-7/+2
| | | | | | | | | | | | | | There is no need to disable support for partitions in the SPL, we can support partitions in SPL perfectly well. This is likely some remnant from old times, so just remove this configuration option. Moreover, the CRC32 chunk size doesn't have to be adjusted anymore, since both the GD and malloc area are in RAM by the time this CRC check can be used and there's plenty of space. Zap this abomination as well. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Move SPL GD and malloc to RAMMarek Vasut2015-08-08-6/+8
| | | | | | | | | | | Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Export bootmode into environment variableMarek Vasut2015-08-08-0/+1
| | | | | | | | setenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for booting from QSPIMarek Vasut2015-08-08-0/+9
| | | | | | | Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for booting from SD/MMCMarek Vasut2015-08-08-0/+14
| | | | | | | | | | Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Remove custom linker scriptMarek Vasut2015-08-08-3/+0
| | | | | | | | Remove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Merge spl_board_init() into board_init_f()Marek Vasut2015-08-08-1/+0
| | | | | | | | | | The code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: enable the Altera SDRAM controller driverDinh Nguyen2015-08-08-0/+5
| | | | | | | Enable the Altera SDRAM driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* usb: USB download gadget and functions config options coherent namingPaul Kocialkowski2015-07-22-3/+3
| | | | | | | | | | | | This introduces a coherent scheme for naming USB download gadget and functions config options. The download USB gadget config option is moved to CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each function's config option is moved to a CONFIG_USB_FUNCTION_ prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* Move default y configs out of arch/board KconfigJoe Hershberger2015-06-25-2/+0
| | | | | | | | | | | | | | | | | | | Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defconfigs... This will cause merge pain if allowed to proliferate. Remove the configs that behave this way from the archs. A few configs still remain, but that is because they only exist as defaults and do not have a proper Kconfig entry. Those appear to be: SPIFLASH DISPLAY_BOARDINFO Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates, drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: remove CONFIG_NET_MULTILars Poeschel2015-06-02-1/+0
| | | | | | | | | CONFIG_NET_MULTI is not used anywhere and thus can safely be removed from the configs. Acked-by: Marek Vasut <marex@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
* ARM: socfpga: abolish CONFIG_SOCFPGAMasahiro Yamada2015-05-07-2/+0
| | | | | | Replace CONFIG_SOCFPGA with CONFIG_ARCH_SOCFPGA. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: socfpga: move SoC sources to mach-socfpgaMasahiro Yamada2015-05-07-1/+1
| | | | | | Our recent trend is to collect SoC files into arch/arm/mach-(SOC). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl mallocDinh Nguyen2015-04-21-1/+1
| | | | | | | We need to adjust the SYS_INIT_RAM_SIZE to have room for the SPL_MALLOC_SIZE. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.hDinh Nguyen2015-04-21-0/+5
| | | | Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KBDinh Nguyen2015-04-21-0/+1
| | | | | | The Cyclone5 SoCFPGA has 64KB of OCRAM for SPL use. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* Kconfig: Move CONFIG_DESIGNWARE_ETH to KconfigSimon Glass2015-04-18-1/+0
| | | | | | | | | | Move this to Kconfig and clean up board config files that use it. Also rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists in drivers/net/Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Version 1: Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* arm: socfpga: Zap board_early_init_f()Marek Vasut2015-03-04-1/+0
| | | | | | | | | | | Zap this unused empty function, no point in having it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Zap checkboard()Marek Vasut2015-03-04-1/+1
| | | | | | | | | | | | | Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* dm: socfpga: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-7/+0
| | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: socfpga: Change watchdog timeoutStefan Roese2014-12-21-1/+1
| | | | | | | | | | | | | | | | The current current watchdog timeout of 12 seconds is a bit small for booting into Linux, especially when using a NFS based rootfs. So lets change this timeout to a more defensive value of 30 seconds. Also we now call the hw_watchdog_init() function so that we override the value already configured from the Preloader. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: DW_SPI: Remove clock info from config headerStefan Roese2014-12-06-4/+0
| | | | | | | | | | | | | Remove the now unnecessary clocking info from the SoCFPGA config header. As this info in now used directly in the SPI driver itself. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add Designware (DW) SPI support to config headerStefan Roese2014-12-06-0/+12
| | | | | | | | | | | | | Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add Cadence QSPI support to config headerStefan Roese2014-12-06-1/+24
| | | | | | | | | | | | | | | | | | | | With this driver enabled for SoCFPGA, access to SPI NOR flash is supported. The configuration (page size, timing info) will be taken from the DT. See socrates as an example. This QSPI supports depends on DT. So QSPI is only enabled if CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* ARM: remove CONFIG_ARMV7 definesMasahiro Yamada2014-11-20-1/+0
| | | | | | | | Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless. Besides, it is never referenced. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-11-11-0/+46
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| * arm: socfpga: Add example config entry for EPCS/EPCQ SPIMarek Vasut2014-10-31-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * arm: socfpga: Add I2C support to SoCFPGAStefan Roese2014-10-30-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds I2C support for the SoCFPGA. Using the designware I2C controller driver. It supports all 4 I2C busses on the SoCFPGA. The designware I2C driver has now been converted to the CONFIG_SYS_I2C framework. So lets enable it on SoCFPGA. Tested on SoCrates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | arm: socfpga: Add example UDC configMarek Vasut2014-11-07-1/+29
|/ | | | | | | | | | | | Add example of an USB UDC configuration with DFU and UMS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Acked-by: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* arm: socfpga: config: Add USB support exampleMarek Vasut2014-10-27-0/+15
| | | | | | | | | | Add example configuration stub for the DWC2 USB controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Pavel Machek <pavel@denx.de>
* arm: socfpga: Zap spl.h and ad-hoc related symsMarek Vasut2014-10-27-6/+11
| | | | | | | | | | | | | Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h contained various ad-hoc symbols, zap those symbols as well and rework the board configuration a little so it doesn't depend on them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Move code from misc_init_r() to arch_early_init_r()Marek Vasut2014-10-27-1/+1
| | | | | | | | | | | | | Move this initialization code to proper place. The misc_init_r() function is called way too late and the platform initialization code should be executed much earlier. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Split SoCFPGA configurationPavel Machek2014-10-06-0/+196
Split the SoCFPGA configuration into SoC-specific part which is common for all boards (socfpga_cyclone5_common.h) and a board specific part. There is currently only one board, which is the generic SoCFPGA board (socfpga_cyclone5.h), but there are more to come. This is necessary due to various features of the boards, which unfortunatelly cannot be autodetected. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
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