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* eeprom: Zap CONFIG_SYS_I2C_MULTI_EEPROMSMarek Vasut2015-11-21-1/+0
| | | | | | | | | | | | | | This option only complicates the code unnecessarily, just use CONFIG_SYS_DEF_EEPROM_ADDR as the default address if there are only five arguments to eeprom {read/write} if this is defined. If CONFIG_SYS_DEF_EEPROM_ADDR is not defined, we mandate all six arguments. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
* Move defaults from config_cmd_default.h to KconfigJoe Hershberger2015-06-25-1/+1
| | | | | | | | | | This sets the default commands Kconfig to match include/config_cmd_default.h commands in the common/Kconfig and removes them from include/configs. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates] Signed-off-by: Tom Rini <trini@konsulko.com>
* net: Remove all references to CONFIG_ETHADDR and friendsJoe Hershberger2015-05-19-9/+0
| | | | | | | | | | We really don't want boards defining fixed MAC addresses in their config so we just remove the option to set it in a fixed way. If you must have a MAC address that was not provisioned, then use the random MAC address functionality. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ppc4xx: Remove 4xx NAND booting supportStefan Roese2014-03-07-66/+4
| | | | | | | | | | | | | | | | | As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* powerpc: ppc4xx: remove redundant CONFIG_4xx definitionMasahiro Yamada2014-01-24-1/+0
| | | | | | | | | | | | We do not have to define CONFIG_4xx in board config headers because it is defined in arch/powerpc/cpu/ppc4xx/config.mk. include/configs/JSE.h defines "CONFIG_4x", not "CONFIG_4xx". I believe it is a typo because "CONFIG_4x" is not used at all in other files. So, I also deleted "CONFIG_4x" in include/configs/JSE.h. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-24-1/+1
|\ | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| * i2c, ppc4xx_i2c: switch to new multibus/multiadapter supportDirk Eibach2013-07-23-1/+1
| | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-14/+1
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* pci: introduce CONFIG_PCI_INDIRECT_BRIDGE optionGabor Juhos2013-06-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
* boards: remove the no longer used CONFIG_EHCI_DCACHEJeroen Hofstee2012-11-20-3/+0
| | | | | | | | | | | | | | | | CONFIG_EHCI_DCACHE was removed by commit b8adb12 "USB: Drop cache flush bloat in EHCI-HCD". Remove the defines from the boards configs as well. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> cc: Marek Vasut <marex@denx.de> cc: Stefan Roese <sr@denx.de> cc: Tom Rini <trini@ti.com> cc: Wolfgang Denk <wd@denx.de> cc: Thierry Reding <thierry.reding@avionic-design.de> cc: Tom Warren <twarren@nvidia.com> cc: Stephen Warren <swarren@nvidia.com> cc: Stefano Babic <sbabic@denx.de>
* nand_spl: store ecc data on the stackScott Wood2012-01-26-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adapt the following patch from spl to nand_spl: Author: Stefano Babic <sbabic@denx.de> Date: Thu Dec 15 10:55:37 2011 +0100 nand_spl_simple: store ecc data on the stack Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM which is likely to contain already loaded data. The patch saves the oob data and the ecc on the stack replacing the fixed address in RAM. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Ilya Yanok <yanok@emcraft.com> CC: Scott Wood <scottwood@freescale.com> CC: Tom Rini <tom.rini@gmail.com> CC: Simon Schwarz <simonschwarzcor@googlemail.com> CC: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com> While nand_spl is on its way out, in favor of spl, there are still many boards using it, and conversions are gradual. This allows us to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now, which would otherwise be likely to linger unreferenced after a conversion. It also eliminates a temporary error in the hawkboard_nand build, since the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but the spl conversion is pending (and may be merged via a different tree). Signed-off-by: Scott Wood <scottwood@freescale.com>
* Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated valueWolfgang Denk2010-10-26-2/+1
| | | | | | | | | | | | | | | | | | CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZEWolfgang Denk2010-10-26-2/+2
| | | | | | | | | | | | | | | | | | CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be some end address; to make the meaning more clear we rename it into CONFIG_SYS_INIT_RAM_SIZE No other code changes are performed in this patch, only minor editing of white space (due to the changed length) and the comments was done, where noticed. Note that the code for the PATI and cmi_mpc5xx board configurations looks seriously broken. Last known maintainers on Cc: Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Denis Peter <d.peter@mpl.ch> Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Makefile: move all Power Architecture boards into boards.cfgWolfgang Denk2010-10-18-0/+4
| | | | | | | | | | Clean up Makefile, and drop a lot of the config.mk files on the way. We now also automatically pick all boards that are listed in boards.cfg (and with all configurations), so we can drop the redundant entries from MAKEALL to avoid building these twice. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Rename TEXT_BASE into CONFIG_SYS_TEXT_BASEWolfgang Denk2010-10-18-1/+1
| | | | | | | | | | | | The change is currently needed to be able to remove the board configuration scripting from the top level Makefile and replace it by a simple, table driven script. Moving this configuration setting into the "CONFIG_*" name space is also desirable because it is needed if we ever should move forward to a Kconfig driven configuration system. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'next' of /home/wd/git/u-boot/nextWolfgang Denk2010-09-28-5/+1
|\ | | | | | | | | | | | | Conflicts: include/ppc4xx.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ppc4xx: Use common NS16550 driver for PPC4xx UARTStefan Roese2010-09-23-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
* | POST cleanup.Michael Zaidman2010-09-21-2/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | - Revives POST for blackfin arch; - Removes redundant code: arch/blackfin/lib/post.c arch/powerpc/cpu/ppc4xx/commproc.c arch/powerpc/cpu/mpc512x/common.c - fixes up the post_word_{load|store} usage. Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com> Acked-by: Detlev Zundel <dzu@denx.de> Tested-by: Anatolij Gustschin <agust@denx.de> List of the maintainers of the affected by patch boards: Cc: Stephan Linz <linz@li-pro.net> Cc: Denis Peter <d.peter@mpl.ch> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Stefan Roese <sr@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Niklaus Giger <niklaus.giger@netstal.com> Cc: Larry Johnson <lrj@acm.org> Cc: Feng Kan <fkan@amcc.com>
* Adds EHCI definitions to sequoia board configuration file.Chris Zhang2010-01-09-1/+15
| | | | | | | Adds required definitions for EHCI support in sequoia configuration file. But still keeps the OHCI as default driver. Signed-off-by: Chris Zhang <chris@seamicro.com>
* ppc4xx: Consolidate pci_pre_init() functionStefan Roese2009-11-19-0/+1
| | | | | | | | | This patch removes the duplicted implementations of the pci_pre_init() function by introducing a weak default function for it. This weak default has a different implementation for some PPC variants. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia: Add chip_config commandStefan Roese2009-10-23-0/+6
| | | | | | | | | | | | | | | This patch removes the Sequoia "bootstrap" command and replaces it with the now common command "chip_config". Please note that the patches with the dynamic PCI sync clock configuration have to be applied, before this one should go in. This is because Sequoia has 2 different bootstrap EEPROMs, and the old bootstrap command configured different values depending on the detected PCI async clock (33 vs. 66MHz). With the PCI sync clock patches, this is not necessary anymore. The PCI sync clock will be configured correctly on-the-fly now. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Sequoia RAM-booting targetStefan Roese2009-06-12-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Disable POST memory test on NAND-booting SequoiaStefan Roese2009-04-16-2/+13
| | | | | | | | | Don't run the memory POST on the NAND-booting version. It will overwrite part of the U-Boot image which is already loaded from NAND to SDRAM. We were just lucky that it booted at all with this SDRAM test enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger2009-01-23-1/+0
| | | | | | | | | | | | | | | | This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-112/+112
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Remove unused CFG_EEPROM_PAGE_WRITE_ENABLE referencesPeter Tyser2008-10-14-1/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-9/+9
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-2/+2
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_NAND in CONFIG_ENV_IS_IN_NANDJean-Christophe PLAGNIOL-VILLARD2008-09-10-2/+2
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Increase image size for NAND boot targetStefan Roese2008-08-30-1/+1
| | | | | | | This is needed since now with HUSH enabled (amcc-common.h) the image read from NAND exceeds the previous limit. Signed-off-by: Stefan Roese <sr@denx.de>
* drivers/mtd: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-1/+1
| | | | | | rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Sequoia has two UARTs in "4-pin" mode. Configure the GPIOs as per ↵Steven A. Falco2008-08-07-6/+6
| | | | | | | | | | | schematic. The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO configuration to match the schematic, and also sets the SDR0_PFC1 register to select the corresponding mode for the UARTs. Signed-off-by: Steven A. Falco <sfalco@harris.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Unify AMCC's board config files (part 3/3)Stefan Roese2008-06-06-156/+17
| | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-3/+3
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"Stefan Roese2008-03-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia: Add device tree (fdt) Linux booting default env variablesStefan Roese2008-03-07-7/+17
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Replace "run load; run update" with conditionalized "run load update".Detlev Zundel2008-03-06-1/+1
| | | | | | | The latter version stops when "run load" fails for whatever reasons rendering the combination *a lot* more secure. Signed-off-by: Detlev Zundel <dzu@denx.de>
* Fix quoting problem (preboot setting) in many board config files.Wolfgang Denk2008-03-03-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Support for ATI Radeon 9200 card on sequoiaAnatolij Gustschin2008-02-22-1/+25
| | | | | | | | Adds configuration option for ATI Radeon 9200 card support to sequoia config file. If CONFIG_VIDEO is enabled, TEXT_BASE should be changed to 0xFFF80000. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* ppc4xx: Beautify configuration files for Sequoia and Korat boardsLarry Johnson2008-02-16-119/+119
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Make Sequoia boot vxWorksNiklaus Giger2008-01-10-0/+1
| | | | | | | | | | | | | | vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia boardLawrence R. Johnson2008-01-04-0/+77
| | | | | | | | | | | | | | Note: this patch changes the configuration of some GPIO registers: Register Old Value New Value --------------- ---------- ---------- DCR GPIO0_TCR 0x0000000F 0x0000F0CF DCR GPIO0_TSRH 0x55005000 0x00000000 DCR GPIO1_TCR 0xC2000000 0xE2000000 DCR GPIO1_TSRL 0x0C000000 0x00200000 DCR GPIO1_ISR2L 0x00050000 0x00110000 Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Move virtual address of POST cache test to bigger addressStefan Roese2007-12-27-1/+1
| | | | | | | | On Sequoia & LWMON5 the virtual address of the POST cache test is now moved to a bigger address. This enables usage of more memory on those boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: fdt: Cleanup setup of cpu node setupStefan Roese2007-12-27-1/+0
| | | | | | | | | Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_BOOTP_SUBNETMASK to Sequoia board configMarkus Klotzbücher2007-12-27-0/+1
| | | | | | | | | | When using dhcp/bootp the "netmask" environment variable is not set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is desireable, so the following patch adds this this option to the board config. Signed-off-by: Markus Klotzbuecher <mk@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-0/+6
| | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Use generic usb-ohci driver for sequoia boardMatthias Fuchs2007-11-09-1/+8
| | | | | | | | This patch makes the sequoia board use the generic usb-ohci driver instead of cpu/ppc4xx/usb_ohci.c. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove cache definition from 4xx board config filesStefan Roese2007-10-31-9/+8
| | | | | | | All 4xx board config files don't need the cache definitions anymore. These are now defined in common headers. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-0/+2
| | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx SequoiaGary Jennejohn2007-08-31-1/+2
| | | | | | | | | | | | | | | | | | | | | The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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