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* ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-0/+2
| | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx SequoiaGary Jennejohn2007-08-31-1/+2
| | | | | | | | | | | | | | | | | | | | | The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Only enable POST FPU test on Sequoia and not RainierStefan Roese2007-08-16-1/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'testing' into workingAndy Fleming2007-08-03-28/+40
|\ | | | | | | | | | | | | | | | | | | Conflicts: CHANGELOG fs/fat/fat.c include/configs/MPC8560ADS.h include/configs/pcs440ep.h net/eth.c
| * include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*.Jon Loeliger2007-07-10-0/+9
| | | | | | | | | | | | | | | | | | Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * include/configs: Use new CONFIG_CMD_* in various s* named board config files.Jon Loeliger2007-07-05-28/+31
| | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | Merged POST framework with the current TOT.Sergei Poselenov2007-07-05-0/+4
|/ | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-2/+15
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| * Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-1/+1
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| * Extend POST support for PPC440Igor Lisitsin2007-06-22-1/+14
| | | | | | | | | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* | ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-1/+0
|/ | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-3/+10
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| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-3/+10
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config fileJeffrey Mann2007-05-07-1/+1
| | | | | | | | | | | | | | | | A '3' got cut off in the formatting of the last patch to automatically change the clock speed of the system clock on sequoia board. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHzJeffrey Mann2007-05-05-1/+3
|/ | | | | | | | | | | The AMCC Secquoia board has been changed in a new revision from using a 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD indicates the difference. This patch reads that bit and uses the correct clock speed for the board. This code is backward compatable will all prior boards. All prior boards will be read as 33.000. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge some AMCC make targets to keep the top-level Makefile smallerStefan Roese2007-03-28-1/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Small Sequoia cleanupStefan Roese2007-03-24-10/+5
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update Sequoia EBC configuration (NOR FLASH)Stefan Roese2007-02-19-2/+2
| | | | | | | As spotted by Matthias Fuchs, the READY input should not be enabled for the NOR FLASH on the Sequoia board. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Remove PCI-PNP configuration from Sequoia/Rainier config fileStefan Roese2007-02-01-1/+1
| | | | | | | | When PCI PNP is enabled the pci pnp configuration routine is called which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some problems with some PCI cards. For now disable the PCI PNP configuration. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update Sequoia (440EPx) config fileStefan Roese2007-01-30-9/+19
| | | | | | | | The config file now handles the 2nd target, the Rainier (440GRx) evaluation board better. Additionally the PPC input clock was adjusted to match the correct value of 33.0 MHz. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-1/+4
| | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Select NAND embedded environment from board configurationStefan Roese2006-11-27-0/+1
| | | | | | | | | | The current NAND Bootloader setup forces the environment variables to be in line with the bootloader. This change enables the configuration to be made in the board include file instead so that it can be individually enabled. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASHStefan Roese2006-11-20-6/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Add board/cpu specific NAND chip select function to 440 NDFCStefan Roese2006-10-20-7/+8
| | | | | Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006
* Add support for AMCC Rainier PPX440GRx eval boardStefan Roese2006-09-13-1/+12
| | | | Patch by Stefan Roese, 13 Sep 2006
* Add NAND environment support for PPC440EPx Sequoia NAND boot configStefan Roese2006-09-12-20/+7
| | | | Patch by Stefan Roese, 12 Sep 2006
* Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese2006-09-07-0/+431
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
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