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* ppc4xx: Unify AMCC's board config files (part 3/3)Stefan Roese2008-06-06-156/+17
| | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-3/+3
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"Stefan Roese2008-03-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia: Add device tree (fdt) Linux booting default env variablesStefan Roese2008-03-07-7/+17
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Replace "run load; run update" with conditionalized "run load update".Detlev Zundel2008-03-06-1/+1
| | | | | | | The latter version stops when "run load" fails for whatever reasons rendering the combination *a lot* more secure. Signed-off-by: Detlev Zundel <dzu@denx.de>
* Fix quoting problem (preboot setting) in many board config files.Wolfgang Denk2008-03-03-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Support for ATI Radeon 9200 card on sequoiaAnatolij Gustschin2008-02-22-1/+25
| | | | | | | | Adds configuration option for ATI Radeon 9200 card support to sequoia config file. If CONFIG_VIDEO is enabled, TEXT_BASE should be changed to 0xFFF80000. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* ppc4xx: Beautify configuration files for Sequoia and Korat boardsLarry Johnson2008-02-16-119/+119
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Make Sequoia boot vxWorksNiklaus Giger2008-01-10-0/+1
| | | | | | | | | | | | | | vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia boardLawrence R. Johnson2008-01-04-0/+77
| | | | | | | | | | | | | | Note: this patch changes the configuration of some GPIO registers: Register Old Value New Value --------------- ---------- ---------- DCR GPIO0_TCR 0x0000000F 0x0000F0CF DCR GPIO0_TSRH 0x55005000 0x00000000 DCR GPIO1_TCR 0xC2000000 0xE2000000 DCR GPIO1_TSRL 0x0C000000 0x00200000 DCR GPIO1_ISR2L 0x00050000 0x00110000 Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Move virtual address of POST cache test to bigger addressStefan Roese2007-12-27-1/+1
| | | | | | | | On Sequoia & LWMON5 the virtual address of the POST cache test is now moved to a bigger address. This enables usage of more memory on those boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: fdt: Cleanup setup of cpu node setupStefan Roese2007-12-27-1/+0
| | | | | | | | | Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_BOOTP_SUBNETMASK to Sequoia board configMarkus Klotzbücher2007-12-27-0/+1
| | | | | | | | | | When using dhcp/bootp the "netmask" environment variable is not set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is desireable, so the following patch adds this this option to the board config. Signed-off-by: Markus Klotzbuecher <mk@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-0/+6
| | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Use generic usb-ohci driver for sequoia boardMatthias Fuchs2007-11-09-1/+8
| | | | | | | | This patch makes the sequoia board use the generic usb-ohci driver instead of cpu/ppc4xx/usb_ohci.c. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove cache definition from 4xx board config filesStefan Roese2007-10-31-9/+8
| | | | | | | All 4xx board config files don't need the cache definitions anymore. These are now defined in common headers. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-0/+2
| | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx SequoiaGary Jennejohn2007-08-31-1/+2
| | | | | | | | | | | | | | | | | | | | | The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Only enable POST FPU test on Sequoia and not RainierStefan Roese2007-08-16-1/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'testing' into workingAndy Fleming2007-08-03-28/+40
|\ | | | | | | | | | | | | | | | | | | Conflicts: CHANGELOG fs/fat/fat.c include/configs/MPC8560ADS.h include/configs/pcs440ep.h net/eth.c
| * include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*.Jon Loeliger2007-07-10-0/+9
| | | | | | | | | | | | | | | | | | Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * include/configs: Use new CONFIG_CMD_* in various s* named board config files.Jon Loeliger2007-07-05-28/+31
| | | | | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | Merged POST framework with the current TOT.Sergei Poselenov2007-07-05-0/+4
|/ | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-2/+15
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| * Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-1/+1
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| * Extend POST support for PPC440Igor Lisitsin2007-06-22-1/+14
| | | | | | | | | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* | ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-1/+0
|/ | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-3/+10
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| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-3/+10
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config fileJeffrey Mann2007-05-07-1/+1
| | | | | | | | | | | | | | | | A '3' got cut off in the formatting of the last patch to automatically change the clock speed of the system clock on sequoia board. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHzJeffrey Mann2007-05-05-1/+3
|/ | | | | | | | | | | The AMCC Secquoia board has been changed in a new revision from using a 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD indicates the difference. This patch reads that bit and uses the correct clock speed for the board. This code is backward compatable will all prior boards. All prior boards will be read as 33.000. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge some AMCC make targets to keep the top-level Makefile smallerStefan Roese2007-03-28-1/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Small Sequoia cleanupStefan Roese2007-03-24-10/+5
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update Sequoia EBC configuration (NOR FLASH)Stefan Roese2007-02-19-2/+2
| | | | | | | As spotted by Matthias Fuchs, the READY input should not be enabled for the NOR FLASH on the Sequoia board. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Remove PCI-PNP configuration from Sequoia/Rainier config fileStefan Roese2007-02-01-1/+1
| | | | | | | | When PCI PNP is enabled the pci pnp configuration routine is called which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some problems with some PCI cards. For now disable the PCI PNP configuration. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update Sequoia (440EPx) config fileStefan Roese2007-01-30-9/+19
| | | | | | | | The config file now handles the 2nd target, the Rainier (440GRx) evaluation board better. Additionally the PPC input clock was adjusted to match the correct value of 33.0 MHz. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-1/+4
| | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Select NAND embedded environment from board configurationStefan Roese2006-11-27-0/+1
| | | | | | | | | | The current NAND Bootloader setup forces the environment variables to be in line with the bootloader. This change enables the configuration to be made in the board include file instead so that it can be individually enabled. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASHStefan Roese2006-11-20-6/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Add board/cpu specific NAND chip select function to 440 NDFCStefan Roese2006-10-20-7/+8
| | | | | Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006
* Add support for AMCC Rainier PPX440GRx eval boardStefan Roese2006-09-13-1/+12
| | | | Patch by Stefan Roese, 13 Sep 2006
* Add NAND environment support for PPC440EPx Sequoia NAND boot configStefan Roese2006-09-12-20/+7
| | | | Patch by Stefan Roese, 12 Sep 2006
* Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese2006-09-07-0/+431
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
generated by cgit v1.1 at 2024-11-01 22:50:16 +0000