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* Merge with /home/sr/git/u-boot/cfi-flashWolfgang Denk2006-04-06-1/+2
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| * * Changes/fixes for drivers/cfi_flash.c:Stefan Roese2006-04-01-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add Intel legacy lock/unlock support to common CFI driver On some Intel flash's (e.g. Intel J3) legacy unlocking is supported, meaning that unlocking of one sector will unlock all sectors of this bank. Using this feature, unlocking of all sectors upon startup (via env var "unlock=yes") will get much faster. - Fixed problem with multiple reads of envronment variable "unlock" as pointed out by Reinhard Arlt & Anders Larsen. - Removed unwanted linefeeds from "protect" command when CFG_FLASH_PROTECTION is enabled. - Changed p3p400 board to use CFG_FLASH_PROTECTION Patch by Stefan Roese, 01 Apr 2006 * Changes/fixes for drivers/cfi_flash.c: - Correctly handle the cases where CFG_HZ != 1000 (several XScale-based boards) - Fix the timeout calculation of buffered writes (off by a factor of 1000) Patch by Anders Larsen, 31 Mar 2006
* | Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)Stefan Roese2006-03-31-4/+8
|/ | | | | | | | | | | | | | | | | | 405 SDRAM: - The SDRAM parameters can now be defined in the board config file and the 405 SDRAM controller values will be calculated upon bootup (see PPChameleonEVB). When those settings are not defined in the board config file, the register setup will be as it is now, so this implementation should not break any current design using this code. Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the TR1 value for the DDR. - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006
* Add support for Prodrive P3P440 board:Stefan Roese2005-11-22-0/+318
- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c - CFG_FLASH_QUIET_TEST added to use the common CFI driver for bank autodetection Patch by Stefan Roese, 22 Nov 2005