| Commit message (Collapse) | Author | Age | Lines |
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Since i.MX7D SDB revB board has some HW changes, we have modify the BSP file to support new pinmux.
1. OTG2 PWR pin is changed to GPIO1_IO07.
2. A enet2_en pin is added for isolating enet2 signals with EPDC, we also add support for enet2.
3. pin6 of 74LV output is changed for CSI PWDN. Set output to high to power down it.
This patch also tries to get the board id and apply changes according with it. Since current
RevB board does not burn GP1 fuse for board id, we have to check the TO rev instead even it is not very
exact. Will update this if any new way implemented.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Windows DeviceIoControl SCSI_PASSTHROUGH is not stable when report media is
not ready.
Use dummy fat file to workaround this issue and avoid windows popup
format dialog.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
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The current 36M offset will conflict with NAND FCB firmware2 when the
nand chip block is 1MB size. This patch change it to 36M + 1M offset,
so the redundant u-boot at firmware2 will not be broken.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The previous 8M address for NAND env might conflict with other boot
parameters as the NAND block size increasing, change it to 36M to avoid
it.
Signed-off-by: Han Xu <b45815@freescale.com>
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In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only.
CM4 image will set the M4 to domain 1 only.
This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and
setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Abstracted the CSF size in imximage from a hardcoded value to a config
setting CONFIG_CSF_SIZE. This configuration is only enabled for secure
boot.
Increased the size of the CSF default allocation to 0x4000. This size
covers the event the worst case of 4906-bits keys.
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Move VIDEO config to the front of EPDC
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable thermal for mx7dsabresd board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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add this parameter in u-boot as a temporary workaround.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit f0beee980914360c8783406ef8694974467eb07b)
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The mx7dsabresd uses new LCD TFT43AB which has 480 x 272 pixels.
Update panel info for this LCD.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e77d667b20956a37de9d367a8914ef2fe79258df)
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To enable the EPDC feature:
1. Uncomments CONFIG_SPLASH_SCREEN and CONFIG_MXC_EPDC settings
in mx7dsabresd.h
2. cd <kernel_dir>/firmware/imx
3. python ihex2bin.py -i epdc_ED060XD4C1_TC.fw.ihex -o epdc_splash.bin
4. cp epdc_splash.bin to [FAT partition on SD card]
Since the EPDC has pinmux conflicts with ENET and QSPI. These two
modules can't work at same time.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 8ba7f88f9efac9f90319b71644d3d1191f535d03)
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Upgrade to upstream way, using power_init_board.
Add pfuze300 support.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Change QSPI FLASH vendor config from to MACRONIX, otherwise the flash
device can't be recognized.
Also change default sf probe parameter to 0:0 which means bus 0, cs 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit f250cf69571851eb092252275418daf8de11a68e)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update board codes to support GPMI NAND flash. Since the GPMI NAND needs
board rework, it is disabled at default. Two ways to enable GPMI NAND:
1. Define CONFIG_SYS_BOOT_NAND for NAND boot case
2. Modify the line 306 in mx7dsabresd.h from QSPI to NAND.
#define CONFIG_SYS_USE_QSPI /* Enable the QSPI flash at default */
to
#define CONFIG_SYS_USE_NAND /* Enable the NAND flash at default */
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5db03facf3add6a95728bc97ac2300003a103932)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable android fastboot, recovery, booti features for mx7d sabresd
board by using new build target: mx7devkandroid_config
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit bfc2b467ddac9c6eccb3f39aad3663a959546b64)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
boards.cfg
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Add i.MX7D SABRESD board BSP codes, with enabled modules:
UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.
Build target: mx7dsabresd_config
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 3bf52a153e2964d4fdc17f0e8cb816686cbb6c2b)
Conflicts:
boards.cfg
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