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dd read and change voltage support for mx6.
For help, pls type "help regul"
Detail command info:
regul list - List all regulators' name
regul show all - Display all regulators' voltage
regul show core - Show core voltage in mV
regul show periph - Show peripheral voltage in mV
regul show <regulator name> - Show regulator's voltage in mV
regul set core <voltage value> - Set core voltage in mV
regul set periph <voltage value> - Set periph voltage in mV
regul set <regulator name> <voltage value> - Set regulator's voltage in
mV
Example:
MX6Q ARM2 U-Boot > regul list
Name Voltage
vddpu
vddcore
vddsoc
vdd2p5
vdd1p1
vdd3p0
MX6Q ARM2 U-Boot > regul show all
Name Voltage
vddpu 1100000
vddcore 1100000
vddsoc 1200000
vdd2p5 2400000
vdd1p1 1100000
vdd3p0 3000000
MX6Q ARM2 U-Boot > regul show periph
Name Voltage
periph: 1100000
MX6Q ARM2 U-Boot > regul show core
Name Voltage
core: 1100000
MX6Q ARM2 U-Boot > regul set core 1100000
Set voltage succeed!
Name Voltage
core: 1100000
Signed-off-by: Terry Lv <r65388@freescale.com>
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Move partition command from nand to sata in mx6 for nand don't need
these partition command.
Signed-off-by: Terry Lv <r65388@freescale.com>
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For ARM2 and Sabreauto, change TTY0 to TTY3 (which is physical UART4)
For SabreSD, Change TTY3 to TTY0 (which is physical UART1)
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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For uImage's size of mx6q is larger than 3M, we enlarge mmc read size to
4M in default env.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include
- TEXT_BASE
- RAM address and size
- Initialization DCD
- MMU related code
Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is
generated, set the board to serial download mode, use sb loader to run the
bootloader.
There is one line in the original DDR initialization script
setmem /32 0x00B00000 = 0x1
however this address can not be accessed by DCD. A try to add it later in
"dram_init" block the boot up. Waiting for IC team to give an explanation
on it. Hold temperorily
The MMU Change can be concluded as the following
- Cacheable and Uncacheable SDRAM allocation changes to
Phys Virtual Size Property
---------- ---------- -------- ----------
0x10000000 0x10000000 256M cacheable
0x80000000 0x20000000 16M uncacheable
0x81000000 0x21000000 240M cacheable
- TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start
of SDRAM. This address makes sure that the text section of U-boot have the
same Physical and Virtural address, thus the PC don't need to change when
MMU is enabled. Also the text section is all allocated in cacheable memory,
which may increase excecution performance.
- Since this SDRAM allocation avoid overlap in physical memory between
cacheable and uncacheable memory, the implementation of __ioremap can be
ignored
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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