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* MLK-10829-2 imx:mx6 support thermal for all mx6Peng Fan2015-05-06-0/+3
| | | | | | | | Move CONFIG_IMX_THERMAL to mx6_common.h Make CONFIG_MXC_OCOTP only depends on CONFIG_CMD_FUSE, since when THERMAL is not implemented, we may use fuse. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10808-4 imx: Move system counter driver to imx-commonYe.Li2015-05-04-2/+9
| | | | | | | | | | | | | Since the system counter driver will also be used by mx6ul, move this timer driver to imx-common and rename it as syscounter.c For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default). GPT timer: CONFIG_GPT_TIMER System counter timer: CONFIG_SYSCOUNTER_TIMER Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2015-04-29-0/+3
| | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640)
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2015-04-29-0/+1
| | | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
* MLK-10448-3 mx6: ccm: Change the clock settings for i.MX6QPYe.Li2015-04-29-0/+3
| | | | | | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 5e4d1537ce9a476c8404126350f05d8976c5aa35) Conflicts: arch/arm/cpu/armv7/mx6/clock.c arch/arm/include/asm/arch-mx6/crm_regs.h include/configs/mx6_common.h
* MLK-10774-1 imx: LDO: add LDO bypassPeng Fan2015-04-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch is from two commits: 1. 748eac71fde78aa0c2e8cb3a3bab94bd994c06f5 ENGR00315499-5: Support i.MX6 1.2GHz via LDO bypass Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. 93d457e4c601ee5266bc30b7dfa5fa1bbfa8500a MLK-9891-1: ARM: imx6: split WDOG_B setting from set_anatop_bypass() function We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Board code is not included, board ldo bypass code will be in bsp update code. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* mx6_common: Do not select esdhc DDR mode for all boardsFabio Estevam2015-03-13-2/+0
| | | | | | | | | | | | CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE should be selected only by boards that really have a DDR-capable eMMC, so remove this option from common code to avoid regressions. Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Tested-by: Stefan Roese <sr@denx.de>
* mmc: fsl_esdhc: Add support for DDR modeVolodymyr Riazantsev2015-02-24-0/+2
| | | | | | | | Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Reviewed-by: York Sun <yorksun@freescale.com>
* imx: mx6: Enable high frequency clock source for GPTYe.Li2014-11-03-0/+1
| | | | | | | Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that 24Mhz OSC clock source will be selected for GPT on all MX6 platforms. Signed-off-by: Ye.Li <B37916@freescale.com>
* mx6: add support of multi-processor commandGabriel Huau2014-08-20-0/+2
| | | | | | | | | This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: drop ARM errata 742230Shawn Guo2014-06-17-1/+0
| | | | | | | | | | | | | | | | | Commit e9fd66defd7e (ARM: mx6: define CONFIG_ARM_ERRATA_742230) enables errata 742230 for imx6, because it helps remove one reboot issue. However, this errata does not really apply on imx6, because Cortex-A9 on imx6 is r2p10 while the errata only applies to revisions r1p0..r2p2. At a later time, commit f71cbfe3ca5d (ARM: Add workaround for Cortex-A9 errata 794072) adds support of errata 794072, which applies to all Cortex-A9 revisions. As the workaround for both errata are exactly same, it makes a lot more sense to select 794072 instead of 742230 for imx6. Since we already enable 794072 for imx6, it's time to drop errata 742230 to avoid confusion. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Nitin Garg <nitin.garg@freescale.com>
* MX6: Enable ARM errata workaround 794072 and 761320Nitin Garg2014-04-07-0/+2
| | | | | | | Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 794072 and 761320. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* mx6: Enable L2 cache supportFabio Estevam2014-02-11-0/+5
| | | | | | | | | | | Add L2 cache support and enable it by default. Configure the L2 cache in the same way as done by FSL kernel: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: soc: Add the required LDO ramp up delayFabio Estevam2014-01-02-0/+1
| | | | | | | | | | When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* ARM: mx6: define CONFIG_ARM_ERRATA_742230Shawn Guo2013-04-17-0/+1
| | | | | | | | | | The ARM errata 742230 - "ARM errata: DMB operation may be faulty" is claimed for Cortex-A9 (r1p0..r2p2). Though i.MX6 uses a newer revision than r2p2, we are seeing a reboot failure on i.MX6 SMP build that can be fixed by applying the workaround for this errata. So for safety, let's define CONFIG_ARM_ERRATA_742230 to enable the workaround on i.MX6. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: mx6: use common CPU errata config optionsStephen Warren2013-03-07-0/+23
Now that U-Boot has common CONFIG_ options to work around some ARM CPU errata, enable the relevant options on MX6, and remove the custom lowlevel_init.S, since it's just duplicated code now. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Jason Liu <r64343@freescale.com>
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