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* ppc4xx: Enable ECC on LWMON5Stefan Roese2008-03-27-5/+1
| | | | | | | | | | | Since all ECC related problems seem to be resolved on LWMON5, this patch now enables ECC support. We have to write the ECC bytes by zeroing and flushing in smaller steps, since the whole 256MByte takes too long for the external watchdog. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"Stefan Roese2008-03-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr@denx.de>
* The patch introduces the alternative configuration of the log buffer for the ↵Yuri Tikhonov2008-03-18-0/+2
| | | | | | | | | | | | | | lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5). To enable this, alternative, configuration the U-Boot board configuration file for lwmon5 includes the definitions of alternative addresses for header (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* Add support for the lwmon5 board reset via GPIO58.Yuri Tikhonov2008-03-18-0/+2
| | | | | Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* The patch adds new POST tests for the Lwmon5 board. These are:Yuri Tikhonov2008-03-18-4/+88
| | | | | | | | | | | * External Watchdog test; * dsPIC tests; * FPGA test; * GDC test; * Sysmon tests. Signed-off-by: Dmitry Rakhchev <rda@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* Replace "run load; run update" with conditionalized "run load update".Detlev Zundel2008-03-06-1/+1
| | | | | | | The latter version stops when "run load" fails for whatever reasons rendering the combination *a lot* more secure. Signed-off-by: Detlev Zundel <dzu@denx.de>
* lwmon5: enable hardware watchdogYuri Tikhonov2008-02-22-2/+1
| | | | | | | | | | | | | Some boards (e.g. lwmon5) may use rather small watchdog intervals, so causing it to reboot the board if U-Boot does a long busy-wait with udelay(). Thus, for these boards we have to restart WD more frequently. This patch splits the busy-wait udelay() into smaller, predefined, intervals, so that the watchdog timer may be resetted with the configurable (CONFIG_WD_PERIOD) interval. Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
* LWMON5: enable hush shell as command line parserWolfgang Denk2008-01-16-0/+6
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Rework Lime support for lwmon5Anatolij Gustschin2008-01-11-0/+16
| | | | | | Rework Lime support for lwmon5 using new video driver Signed-off-by: Anatolij Gustschin <agust@denx.de>
* ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymoreStefan Roese2008-01-09-7/+12
| | | | | | | This patch configures the LWMON5 port to use d-cache as init-ram and the unused GPT0_COMP6 as POST WORD storage. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Move virtual address of POST cache test to bigger addressStefan Roese2007-12-27-1/+1
| | | | | | | | On Sequoia & LWMON5 the virtual address of the POST cache test is now moved to a bigger address. This enables usage of more memory on those boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-1/+1
| | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove cache definition from 4xx board config filesStefan Roese2007-10-31-9/+0
| | | | | | | All 4xx board config files don't need the cache definitions anymore. These are now defined in common headers. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: lwmon5: Some further GPIO config changesStefan Roese2007-10-23-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yetStefan Roese2007-10-02-0/+5
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of /home/stefan/git/u-boot/lwmon5Stefan Roese2007-09-27-4/+5
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| * ppc4xx: Change lwmon5 default environment to support Linux RTCStefan Roese2007-08-29-4/+5
| | | | | | | | | | | | | | | | | | | | The Linux PCF8563 RTC driver doesn't do autoprobing, so we need to supply the RTC I2C address as bootline parameter. This patch adds support for this rtc probing parameter to the bootargs: "rtc-pcf8563.probe=0,0x51" Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test)Stefan Roese2007-09-27-1/+1
|/ | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add RTC POST test to lwmon5 board configurationStefan Roese2007-08-24-7/+8
| | | | | | | | Since this RTC POST test is taking quite a while to complete it's only initiated upon special keypress same as the complete memory POST. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change GPIO signal for watchdog triggering on lwmon5Stefan Roese2007-08-24-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 boardStefan Roese2007-08-23-6/+9
| | | | | | | | | | | This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5 board. Now the "eeprom" command can be used to read/write from/to this device. Additionally a new command was added "eepromwp" to en-/disable the write-protect of this 2nd EEPROM. The 1st EEPROM is not affected by this write-protect command. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove unused option CFG_INIT_RAM_OCMStefan Roese2007-08-22-1/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/u-boot-ppc4xxStefan Roese2007-08-21-30/+55
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| * lib_ppc: make board_add_ram_info weakKim Phillips2007-08-18-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | platforms wishing to display RAM diagnostics in addition to size, can do so, on one line, in their own board_add_ram_info() implementation. this consequently eliminates CONFIG_ADD_RAM_INFO. Thanks to Stefan for the hint. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-08-14-28/+37
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| | * Merge branch 'testing' into workingAndy Fleming2007-08-03-27/+39
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: CHANGELOG fs/fat/fat.c include/configs/MPC8560ADS.h include/configs/pcs440ep.h net/eth.c
| | | * include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*.Jon Loeliger2007-07-10-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| | | * include/configs: Catch some CONFIG_CMD_* conversion stragglers.Jon Loeliger2007-07-08-27/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use new CONFIG_CMD_* in lwmon5.h board config file. Fix CONFIG_CMD_* typo braindamage in omap1510inn.h Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * | | ppc4xx: Update lwmon5 POST configurationStefan Roese2007-08-10-2/+19
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)Stefan Roese2007-08-21-3/+11
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the matrix keyboard on the lwmon5 board. Since the implementation in the dsPCI is kind of compatible with the "old" lwmon board, most of the code is copied from the lwmon board directory. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Update 440EPx lwmon5 board supportStefan Roese2007-07-31-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | - Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: lwmon5: Update Lime initializationAnatolij Gustschin2007-07-26-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change Lime SDRAM initialization to now support 100MHz and 133MHz (if enabled). Also the framebuffer is initialized to display a blue rectangle with a white border. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: lwmon5: Support for 128 MByte NOR FLASH addedStefan Roese2007-07-24-4/+6
| | | | | | | | | | | | | | | | | | | | | The used Intel NOR FLASH chips have internally two dies, and are now treated as two seperate chips. Signed-off-by: Stefan Roese <sr@denx.de>
* | | POST: Add ECC POST for the lwmon5 boardPavel Kolesnikov2007-07-20-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ECC Post test for the Lwmon5 board based on PPC440EPx to U-Boot. Signed-off-by: Pavel Kolesnikov <concord@emcraft.com> Acked-by: Yuri Tikhonov <yur@emcraft.com> Acked-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Update lwmon5 default environmentStefan Roese2007-07-06-0/+2
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Update lwmon5 boardStefan Roese2007-07-06-0/+1
|/ / | | | | | | | | | | | | Add unlock=yes environment variable to default variables to unlock the CFI flash by default. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update lwmon5 boardStefan Roese2007-07-04-2/+14
|/ | | | | | | | | | - Add optional ECC generation routine to preserve existing RAM values. This is needed for the Linux log-buffer support - Add optional DDR2 setup with CL=4 - GPIO50 not used anymore - Lime register setup added Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-2/+2
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| * Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-2/+2
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* | ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-1/+0
|/ | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Change lwmon5 port to work with recent 440 exception reworkStefan Roese2007-06-15-0/+1
| | | | | | Now CONFIG_440 has to be defined in all PPC440 board config files. Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Add initial lwmon5 board supportStefan Roese2007-06-15-0/+437
This patch adds initial support for the Liebherr lwmon5 board euqipped with an AMCC 440EPx PowerPC. Signed-off-by: Stefan Roese <sr@denx.de>
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