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* x86: crownbay: Enable CONFIG_PCH_GBEBin Meng2015-09-09-3/+0
| | | | | | | | Now that we have converted the pch_gbe driver to driver moel, enable it on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Convert to use CONFIG_DM_ETH for E1000Bin Meng2015-09-09-1/+0
| | | | | | | | | Since E1000 driver has been converted to driver model, enable it on Intel Crown Bay. But the Intel Topcliff GbE driver has not been converted to driver model yet, disable it for now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* x86: crownbay: Enable on-board SMSC superio keyboard controllerBin Meng2015-08-26-3/+0
| | | | | | | | | | | | | | | So far we only enabled one legacy serial port on the SMSC LPC47m superio chipset on Intel Crown Bay board. As the board also has dual PS/2 ports routed out, enable the keyboard controller which is i8042 compatible so that we can use PS/2 keyboard and mouse. In order to make PS/2 keyboard work with the VGA console, remove CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode using PIRQ routing table, adjust the mask in the device tree to reserve irq12 which is used by PS/2 mouse. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boardsBin Meng2015-08-26-1/+0
| | | | | | | It looks that x86 chipset always contains a host bridge at pci b.d.f 0.0.0, so enable this for all boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* net: Move CONFIG_E1000 options to KconfigSimon Glass2015-08-21-1/+0
| | | | | | | | Move config for the E1000 Ethernet driver to Kconfig and tidy up affected boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* x86: Move CONFIG_X86_SERIAL to KconfigSimon Glass2015-08-05-1/+0
| | | | | | | Move this config option to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: crownbay: Enable graphics supportBin Meng2015-07-14-7/+7
| | | | | | | | | | | Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.hBin Meng2015-06-04-2/+0
| | | | | | | | | | | | | | | Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect DRAM size printed when booting from coreboot, like this: CPU: x86, vendor Intel, device 663h DRAM: 636 KiB Using default environment Change it to 8 which should be enough for both coreboot and bare cases, and move it to x86-common.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-0/+1
| | | | | | | | Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.hBin Meng2015-04-29-4/+0
| | | | | | | | | | Since all x86 boards use spi flash as its bootloader storage media, it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option. So far only minnowmax board does not support it so undefine it in its board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Enable saving environment in SPI flashBin Meng2015-03-24-0/+8
| | | | | | | Saving U-Boot's environment in SPI flash on Intel CrownBay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sg@chromium.org>
* x86: crownbay: Enable Intel Topcliff GMAC supportBin Meng2015-03-24-0/+4
| | | | | | | | Intel Crown Bay board has one ethernet port connected from Intel Topcliff PCH. Enable it in the board configuration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to KconfigBin Meng2015-01-13-2/+0
| | | | | | | | Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Rename coreboot-serial to x86-serialBin Meng2014-12-18-1/+1
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SDHCI supportBin Meng2014-12-18-0/+6
| | | | | | | | | There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Enable Intel E1000 NIC supportBin Meng2014-12-18-0/+1
| | | | | | | | | We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-0/+2
| | | | | | | | | The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add crownbay defconfig and config.hBin Meng2014-12-18-0/+52
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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