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path: root/include/configs/coreboot.h
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* ahci: convert to use libata functions and definitionsRob Herring2013-09-06-0/+1
| | | | | | | | | | | | | libata already has similar functions as implemented in the ahci code. Refactor the code to use the libata variants and remove the dependency on ata.h. Convert some defines to use the version from libata.h. Also, remove some unnecessary memset's of bss data. This is a step toward hopefully merging ahci.c and dw_ahsata.c which are essentially the same driver. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* x86: config: Add tracing optionsSimon Glass2013-06-26-0/+7
| | | | | | Add configs to enable tracing when it is needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Reflect the name changes of LPC TPM configsTom Wai-Hong Tam2013-06-03-1/+2
| | | | | | | | The new name is more aligned with Linux kernel's naming of TPM driver. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable LZO for coreboot, remove zlib, gzipSimon Glass2013-05-13-0/+4
| | | | | | We don't use zlib and gzip but do use lzo, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable bootstage for corebootSimon Glass2013-05-13-0/+9
| | | | | | | This is a convenient way of finding out where boottime is going. Enable it for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Re-enable PCAT timer 2 for beepingSimon Glass2013-05-13-0/+1
| | | | | | | | While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add TSC timerSimon Glass2013-05-13-3/+1
| | | | | | | | | | | | | | This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Init PCI before SPISimon Glass2013-04-15-0/+1
| | | | | | | | | Since the ICH SPI controller uses PCI, we must ensure that PCI is available before it is inited. This fixes the current "ICH SPI: Cannot find device" message on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-03-20-3/+11
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| * x86: Enable time command for corebootSimon Glass2013-03-19-0/+2
| | | | | | | | | | | | | | This command is useful for measuring SPI flash load times and the like. Enable gettime as well to obtain absolute time tick values. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Enable SPI flash support for corebootSimon Glass2013-03-19-3/+9
| | | | | | | | | | | | Turn on SPI flash support and related commands. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: Enable USB features for corebootSimon Glass2013-03-18-0/+17
|/ | | | | | Enable PCI EHCI, storage, keyboard and Ethernet for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable CONFIG_OF_CONTROL on corebootSimon Glass2013-03-04-0/+6
| | | | | | | Make use of a device tree on coreboot boards, and set the default to link. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTORSimon Glass2013-02-14-1/+0
| | | | | | | Invert the polarity of this option to simplify the Makefile logic. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Gabe Black <gabeblack@chromium.org>
* x86: coreboot: Enable io commandSimon Glass2012-12-26-0/+1
| | | | | | Enable the io command for x86 on coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix coreboot config to boot on ChromebookSimon Glass2012-12-06-14/+12
| | | | | | | | | | The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Turn on support for EFI's GPT in the coreboot configGabe Black2012-12-06-0/+3
| | | | | | | This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Enable video displaySimon Glass2012-12-06-2/+8
| | | | | | Enable the display on coreboot, using CFB. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-06-1/+1
| | | | | | | | | This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable CONFIG_CMD_ZBOOT for corebootSimon Glass2012-12-06-0/+3
| | | | | | Enable this option to support booting a zImage. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable ICH6 GPIO controller for corebootSimon Glass2012-12-06-0/+4
| | | | | | Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass2012-11-30-0/+1
| | | | | | This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Select stdio devices for corebootSimon Glass2012-11-30-0/+12
| | | | | | | We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Enable LPC TPMSimon Glass2012-11-28-0/+4
| | | | | | Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove coreboot start16 codeSimon Glass2012-11-28-1/+1
| | | | | | | Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Put global data on the stackGraeme Russ2012-11-28-3/+2
| | | | | | | | | | Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: config: Enable AHCI support for corebootSimon Glass2012-11-02-0/+22
| | | | | | Enable AHCI driver for Intel SATA devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* config: Enable CBFS, ext4 for corebootSimon Glass2012-10-22-0/+3
| | | | | | Enable Coreboot and EXT4 Filesystems on the coreboot board. Signed-off-by: Simon Glass <sjg@chromium.org>
* serial: Remove CONFIG_SERIAL_MULTI from config filesMarek Vasut2012-10-15-1/+0
| | | | | | | | | | | | | Remove any notion of CONFIG_SERIAL_MULTI from board config files. Since CONFIG_SERIAL_MULTI is now enabled by default, it is useless to specify this config option in the board config files. Therefore remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* configs: Remove CONFIG_NET_MULTI from board filesFabio Estevam2012-02-12-6/+0
| | | | | | | | | | | | | | | | | | CONFIG_NET_MULTI is not used anymore, so remove it from board files. Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kumar Gala <kumar.gala@freescale.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefano Babic <sbabic@denx.de> Tested-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Heiko Schocher <hs@denx.de>
* x86: Initial commit for running as a coreboot payloadGabe Black2011-12-19-0/+225
Add a target for running u-boot as a coreboot payload in boards.cfg, a board, CPU and a config. This is a skeleton implementation which always reports the size of memory as 64 MB. Signed-off-by: Gabe Black <gabeblack@chromium.org>
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