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* 4xx: add missing CONFIG_SYS_SRAM_SIZE definitionWolfgang Denk2010-09-19-0/+1
| | | | | | | | | | | | A number of boards define CONFIG_SYS_SRAM_BASE but fail to define CONFIG_SYS_SRAM_SIZE which is needed when cleaning up the code that prints this information with the bdinfo command. Add the missing deinitions. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx/Canyonlands added USB board callbacksRupjyoti Sarmah2010-07-23-0/+8
| | | | | | | | | | Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell <dmitchell@appliedmicro.com> Signed-off-by: Rupjyoti Sarmah <rsarmah@appliedmicro.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Canyonlands: Change EBC bus config to drive always (no high-z)Stefan Roese2009-11-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem only seen very occasionally on Canyonlands. The NOR flash interface (CFI driver) doesn't work reliably in all cases. Erasing and/or programming sometimes doesn't work. Sometimes with an error message, like "flash not erased" when trying to program an area that should have just been erased. And sometimes without any error messages. As mentioned above, this problem was only seen rarely and with some PLL configuration (CPU speed, EBC speed). Now I spotted this problem a few times, when running my Canyonlands with the following setup (chip_config): 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 Changing the EBC configuration to not release the bus into high impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1 in EBC0_CFG) seems to fix this problem. I haven't seen any failure anymore with this patch applied. Signed-off-by: Stefan Roese <sr@denx.de> Cc: David Mitchell <dmitchell@amcc.com> Cc: Jeff Mann <MannJ@embeddedplanet.com>
* ppc4xx: Fix "chip_config" command for AMCC ArchesStefan Roese2009-08-18-0/+4
| | | | | | | | | | This patch fixes the "chip_config" command for I2C bootstrap EEPROM configuration. First it changes the I2C bootstrap EEPROM address to 0x54 as this is used on Arches (instead of 0x52 on Canyonlands/ Glacier). Additionally, the NAND bootstrap settings are removed for Arches since Arches doesn't support NAND-booting. Signed-off-by: Stefan Roese <sr@denx.de>
* Add "chip_config" command for PPC4xx bootstrap configurationStefan Roese2009-07-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic command for programming I2C bootstrap eeproms on PPC4xx. An implementation for Canyonlands board is included. The command name is intentionally chosen not to be PPC4xx specific. This way other CPU's/SoC's can implement a similar command under the same name, perhaps with a different syntax. Usage on Canyonlands: => chip_config Available configurations (I2C address 0x52): 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 *** 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88 => chip_config 600-nor Using configuration: 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 done (dump via 'i2c md 52 0.1 10') Reset the board for the changes to take effect Other 4xx boards will be migrated to use this command soon as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Dirk Eibach <eibach@gdsys.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* Canyonlands SATA harddisk driverKazuaki Ichinohe2009-07-19-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a SATA harddisk driver for the canyonlands. This patch is kernel driver's porting. This patch corresponded to not cmd_scsi but cmd_sata. This patch divided an unused member with ifndef __U_BOOT__ in the structure. [environment variable, boot script] setenv bootargs root=/dev/sda7 rw setenv bootargs ${bootargs} console=ttyS0,115200 ext2load sata 0:2 0x400000 /canyonlands/uImage ext2load sata 0:2 0x800000 /canyonlands/canyonlands.dtb fdt addr 0x800000 0x4000 bootm 0x400000 - 0x800000 If you drive SATA-2 disk on Canyonlands, you must change parts from PI2PCIE212 to PI2PCIE2212 on U25. We confirmed to boot by using following disks: 1.Vendor: Fujitsu Type: MHW2040BS 2.Vendor: Fujitsu Type: MHW2060BK 3.Vendor: HAGIWARA SYS-COM:HFD25S-032GT 4.Vendor: WesternDigital Type: WD3200BJKT (CONFIG_LBA48 required) 5.Vendor: WesternDigital Type: WD3200BEVT (CONFIG_LBA48 required) 6.Vendor: Hitachi Type: HTS543232L9A300 (CONFIG_LBA48 required) 7.Vendor: Seagate Type: ST31000333AS (CONFIG_LBA48 required) 8.Vendor: Transcend Type: TS32GSSD25S-M 9.Vendor: MTRON Type: MSD-SATA1525-016 Signed-off-by: Kazuaki Ichinohe <kazuichi at fsi.co.jp>
* ppc4xx: Fix FDT EBC mappings on CanyonlandsFelix Radensky2009-07-08-0/+2
| | | | | | | | | | This patch fixes 2 problems with FDT EBC mappings on Canyonlands. First, NAND EBC mapping was missing, making Linux NAND driver unusable on this board. Second, NOR remapping code assumed that NOR is always on CS0, however when booting from NAND NOR is on CS3. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger2009-01-23-1/+0
| | | | | | | | | | | | | | | | This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-1/+1
| | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correctly configure the GPIO pin muxing on ArchesStefan Roese2008-10-31-1/+11
| | | | | | | Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO pin multiplexing correctly Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-17/+205
| | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-102/+102
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Remove unused CFG_EEPROM_PAGE_WRITE_ENABLE referencesPeter Tyser2008-10-14-1/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-9/+9
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-3/+3
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_NAND in CONFIG_ENV_IS_IN_NANDJean-Christophe PLAGNIOL-VILLARD2008-09-10-2/+2
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/mtd: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-1/+1
| | | | | | rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Unify AMCC's board config files (part 2/3)Stefan Roese2008-06-06-156/+17
| | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix Canyonlands and Glacier default environment for fdt usageStefan Roese2008-04-22-10/+13
| | | | | | | | | | | This patch fixes the Canyonlands and Glacier default environment to better fit to the arch/powerpc device-tree kernels. The variables dealing with arch/ppc booting are removed, since these boards are supported only in arch/powerpc. Glacier uses the same config file as Canyonlands. Also, the Glacier now uses non-FPU rootpath, since 460GT has no FPU. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change Canyonlands to support booting from 2k page NAND devicesStefan Roese2008-04-18-10/+16
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix Canyonlands default environment to work with new image supportStefan Roese2008-04-09-7/+5
| | | | | | | Since the new image support checks for image overwriting, the default environment needs to get adjusted to use correct addresses. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revisionStefan Roese2008-03-28-0/+1
| | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch displays the current configuration upon bootup and changes the PCIe init loop, to only initialize the availabel PCIe slots. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Glacier 406GT eval board supportStefan Roese2008-03-27-11/+114
| | | | | | | | | | | | | | This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval boardStefan Roese2008-03-15-22/+46
| | | | | | | This patch adds USB OHCI support to the Canyonlands board port. It also enables EXT2 support. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-8/+81
| | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Canyonlands support (460EX) (2/3)Stefan Roese2008-03-15-0/+470
This patch adds support for the AMCC Canyonlands 460EX evaluation board. Signed-off-by: Stefan Roese <sr@denx.de>
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