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* Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* Move CONFIG_OF_LIBFDT to KconfigSimon Glass2016-03-14-1/+0
| | | | | | Move this option to Kconfig and tidy up existing boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* secure_boot: include/configs: move definition of CONFIG_CMD_BLOBAneesh Bansal2016-01-27-5/+0
| | | | | | | | | | CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* secure_boot: include/configs: make secure boot header file uniformAneesh Bansal2016-01-27-1/+2
| | | | | | | | | | | | | | The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* sf: Move SPI flash drivers to defconfigBin Meng2015-11-25-1/+0
| | | | | | | | There are already Kconfig options for SPI flash drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* spi: Move SPI drivers to defconfigBin Meng2015-11-25-1/+0
| | | | | | | | There are already Kconfig options for SPI drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* ns16550: move CONFIG_SYS_NS16550 to KconfigThomas Chou2015-11-21-1/+0
| | | | | | Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* common/board_f.c: change the macro name and remove it for PPC platformsGong Qianyu2015-10-29-1/+0
| | | | | | | | | | For most PPC platforms, they will call the first get_clocks() in init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is then defined to call the second get_clocks(), which should be redundant for PPC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* common/board_f.c: modify the macro to use get_clocks() more commonGong Qianyu2015-10-24-0/+1
| | | | | | get_clocks() should not be limited by ESDHC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
* arm, powerpc: select SYS_GENERIC_BOARDMasahiro Yamada2015-10-24-1/+0
| | | | | | | | | | | We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* cmd: Convert CONFIG_CMD_ELF to KconfigBin Meng2015-10-21-1/+0
| | | | | | Convert CONFIG_CMD_ELF to Kconfig and tidy up affected boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* powerpc: configs: Fix init_ram physical address for several boardsYork Sun2015-09-01-1/+1
| | | | | | | | For e6500 and e5500 SoCs, it was intended to put init_ram address in ccsr reserved space. It is no longer true since SerDes module took the space. Move it to another reserved space at CCSR + 0x03c000. Signed-off-by: York Sun <yorksun@freescale.com>
* net: Move CONFIG_E1000 options to KconfigSimon Glass2015-08-21-1/+0
| | | | | | | | Move config for the E1000 Ethernet driver to Kconfig and tidy up affected boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Move defaults from config_cmd_default.h to KconfigJoe Hershberger2015-06-25-4/+0
| | | | | | | | | | This sets the default commands Kconfig to match include/config_cmd_default.h commands in the common/Kconfig and removes them from include/configs. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates] Signed-off-by: Tom Rini <trini@konsulko.com>
* Move default y configs out of arch/board KconfigJoe Hershberger2015-06-25-1/+0
| | | | | | | | | | | | | | | | | | | Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defconfigs... This will cause merge pain if allowed to proliferate. Remove the configs that behave this way from the archs. A few configs still remain, but that is because they only exist as defaults and do not have a proper Kconfig entry. Those appear to be: SPIFLASH DISPLAY_BOARDINFO Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates, drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: remove CONFIG_NET_MULTILars Poeschel2015-06-02-1/+0
| | | | | | | | | CONFIG_NET_MULTI is not used anywhere and thus can safely be removed from the configs. Acked-by: Marek Vasut <marex@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
* net: Move the CMD_NET config to defconfigsJoe Hershberger2015-06-01-1/+0
| | | | | | | | | | | This also selects CONFIG_NET for any CONFIG_CMD_NET board. Remove the imx default for CONFIG_NET. This moves the config that was defined by 60296a8 (commands: add more command entries in Kconfig). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* Move setexpr to KconfigJoe Hershberger2015-06-01-1/+0
| | | | | | | | | | | Another shell scripting command that has not been moved. Moved using tools/moveconfig.py using these settings: CMD_SETEXPR bool n y Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* board/t2080rdb: enable CONFIG_PHY_AQUANTIAShengzhou Liu2015-04-20-1/+1
| | | | | | | CONFIG_PHY_AQ1202 is no longer needed, use CONFIG_PHY_AQUANTIA. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t2080rdb: update ddr to support 1866MT/sShengzhou Liu2015-04-20-0/+5
| | | | | | | | Support SODIMM D3XP12081XL10AA 1866MT/s on T2080RDB. Enable CONFIG_CMD_MEMTEST as well. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t208xrdb: VID supportYing Zhang2015-04-20-0/+11
| | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* nand: Remove CONFIG_MTD_NAND_VERIFY_WRITEPeter Tyser2015-03-30-1/+0
| | | | | | | | | The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur2014-12-15-0/+16
| | | | | | | | | Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* config: remove redundant CONFIG_SYS_PROMPT definesMasahiro Yamada2014-11-23-1/+0
| | | | | | | | Since commit 0defddc851ed (config: Add a default CONFIG_SYS_PROMPT), each board header does not need to define CONFIG_SYS_PROMPT as long as it uses the default prompt "=> ". Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc85xx: configs - Enable blob command in freescale platformsRuchika Gupta2014-10-16-0/+1
| | | | | | | | Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: configs - Add hash command in freescale platformsRuchika Gupta2014-10-16-0/+7
| | | | | | | | | Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* include: remove CONFIG_SPL/CONFIG_TPL definition in config headersMasahiro Yamada2014-07-30-1/+0
| | | | | | | | | Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig. Remove the redundant definition in config headers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* include: define CONFIG_SPL and CONFIG_TPL as 1Masahiro Yamada2014-07-30-1/+1
| | | | | | | | | | | | | | | | We are about to switch to Kconfig in the next commit. But there are something to get done beforehand. In Kconfig, include/generated/autoconf.h defines boolean CONFIG macros as 1. CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1. Otherwise, when switching to Kconfig, the build log would be sprinkled with warning messages like this: warning: "CONFIG_SPL" redefined [enabled by default] Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board/freescale: use generic board architecture for t2080qds and t2080rdbShengzhou Liu2014-07-23-0/+2
| | | | | | Tested with NOR boot and NAND boot on T2080QDS and T2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/ifc: fix invalid CSn FTIM2.TCH settingShaohui Xie2014-07-22-1/+1
| | | | | | | | | On some platforms, CSn FTIM2.TCH is set to zero which is invalid, an invalid hold time makes DUT timing variances, whether it works or not on luck. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE bootLiu Gang2014-05-16-5/+5
| | | | | | | | | | | | | | | | | The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations. The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff40000 base address and 0xc0000 size, it should be extended to 1MB size and the base address can be aligned with the size. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: configs: remove c=ffe from default environmentKim Phillips2014-05-16-2/+1
| | | | | | | | | | | AFAICT, c=ffe does nothing and was a typo from the original commit d17123696c6180ac8b74fbd318bf14652623e982 "powerpc/p4080: Add support for the P4080DS board" and just kept on getting duplicated in subsequently added board config files. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Edward Swarthout <ed.swarthout@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t208x: enable errata A006261, A006593, A006379Shengzhou Liu2014-05-13-0/+1
| | | | | | | Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* config: remove platform CONFIG_SYS_HZ definition part 4Masahiro Yamada2014-05-12-1/+0
| | | | | | | Some new boards define CONFIG_SYS_HZ again! Remove. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Bo Shen <voice.shen@atmel.com>
* board/t2080rdb: some update for t2080rdbShengzhou Liu2014-04-22-4/+9
| | | | | | | | | | | | - update readme. - add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE. - update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank. - fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t208xrdb: Add support of 2-stage NAND/SPI/SD bootShengzhou Liu2014-04-22-17/+91
| | | | | | | | | | | Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot sizePrabhakar Kushwaha2014-04-22-1/+1
| | | | | | | | | U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_SYS_MONITOR_LEN to reflect the same. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/T208xRDB: add mtdparts suppportShengzhou Liu2014-04-22-0/+16
| | | | | | | | We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-5/+5
| | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* freescale: pblimage: refactor CONFIG_SYS_FSL_PBL_{PBI, RCW}Masahiro Yamada2014-03-12-2/+2
| | | | | | | | | | Pull out "$(SRCTREE)/" from CONFIG_SYS_FSL_PBL_PBI and CONFIG_SYS_FSL_PBL_RCW and push it into the top Makefile. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/t2080rdb: Add T2080PCIe-RDB board supportShengzhou Liu2014-03-07-0/+779
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-12-27 17:26:23 +0000