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path: root/include/configs/T208xRDB.h
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* mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur2014-12-15-0/+16
| | | | | | | | | Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* config: remove redundant CONFIG_SYS_PROMPT definesMasahiro Yamada2014-11-23-1/+0
| | | | | | | | Since commit 0defddc851ed (config: Add a default CONFIG_SYS_PROMPT), each board header does not need to define CONFIG_SYS_PROMPT as long as it uses the default prompt "=> ". Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc85xx: configs - Enable blob command in freescale platformsRuchika Gupta2014-10-16-0/+1
| | | | | | | | Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: configs - Add hash command in freescale platformsRuchika Gupta2014-10-16-0/+7
| | | | | | | | | Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* include: remove CONFIG_SPL/CONFIG_TPL definition in config headersMasahiro Yamada2014-07-30-1/+0
| | | | | | | | | Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig. Remove the redundant definition in config headers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* include: define CONFIG_SPL and CONFIG_TPL as 1Masahiro Yamada2014-07-30-1/+1
| | | | | | | | | | | | | | | | We are about to switch to Kconfig in the next commit. But there are something to get done beforehand. In Kconfig, include/generated/autoconf.h defines boolean CONFIG macros as 1. CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1. Otherwise, when switching to Kconfig, the build log would be sprinkled with warning messages like this: warning: "CONFIG_SPL" redefined [enabled by default] Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board/freescale: use generic board architecture for t2080qds and t2080rdbShengzhou Liu2014-07-23-0/+2
| | | | | | Tested with NOR boot and NAND boot on T2080QDS and T2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/ifc: fix invalid CSn FTIM2.TCH settingShaohui Xie2014-07-22-1/+1
| | | | | | | | | On some platforms, CSn FTIM2.TCH is set to zero which is invalid, an invalid hold time makes DUT timing variances, whether it works or not on luck. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE bootLiu Gang2014-05-16-5/+5
| | | | | | | | | | | | | | | | | The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations. The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff40000 base address and 0xc0000 size, it should be extended to 1MB size and the base address can be aligned with the size. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: configs: remove c=ffe from default environmentKim Phillips2014-05-16-2/+1
| | | | | | | | | | | AFAICT, c=ffe does nothing and was a typo from the original commit d17123696c6180ac8b74fbd318bf14652623e982 "powerpc/p4080: Add support for the P4080DS board" and just kept on getting duplicated in subsequently added board config files. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Edward Swarthout <ed.swarthout@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t208x: enable errata A006261, A006593, A006379Shengzhou Liu2014-05-13-0/+1
| | | | | | | Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* config: remove platform CONFIG_SYS_HZ definition part 4Masahiro Yamada2014-05-12-1/+0
| | | | | | | Some new boards define CONFIG_SYS_HZ again! Remove. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Bo Shen <voice.shen@atmel.com>
* board/t2080rdb: some update for t2080rdbShengzhou Liu2014-04-22-4/+9
| | | | | | | | | | | | - update readme. - add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE. - update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank. - fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t208xrdb: Add support of 2-stage NAND/SPI/SD bootShengzhou Liu2014-04-22-17/+91
| | | | | | | | | | | Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot sizePrabhakar Kushwaha2014-04-22-1/+1
| | | | | | | | | U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_SYS_MONITOR_LEN to reflect the same. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/T208xRDB: add mtdparts suppportShengzhou Liu2014-04-22-0/+16
| | | | | | | | We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-5/+5
| | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* freescale: pblimage: refactor CONFIG_SYS_FSL_PBL_{PBI, RCW}Masahiro Yamada2014-03-12-2/+2
| | | | | | | | | | Pull out "$(SRCTREE)/" from CONFIG_SYS_FSL_PBL_PBI and CONFIG_SYS_FSL_PBL_RCW and push it into the top Makefile. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/t2080rdb: Add T2080PCIe-RDB board supportShengzhou Liu2014-03-07-0/+779
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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