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* powerpc/t104xrdb: Update DDR initialization related settingsPriyanka Jain2014-03-07-1/+1
| | | | | | | | | | | | | | | | | | Update following DDR related settings for T1040RDB, T1042RDB_PI -Correct number of chip selects to two as t1040 supports two Chip selects. -Update board_specific_parameters udimm structure with settings derived via calibration. -Update ddr_raw_timing sructure corresponding to DIMM. -Set ODT to off. Typically on FSL board, ODT is set to 75 ohm, but on T104xRDB, on setting this , DDR instability is observed. Board-level debugging is in progress. Verified the updated settings to be working fine with dual-ranked Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* config: remove platform CONFIG_SYS_HZ definition part 3Masahiro Yamada2014-02-19-1/+0
| | | | | | | | This commit removes platform CONFIG_SYS_HZ definition for the remainders of part1 (commit cdb23792) and part2 (commit f232950f). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rob Herring <rob.herring@calxeda.com>
* powerpc/t104xrdb: Add basic ethernet supportPriyanka Jain2014-02-03-1/+4
| | | | | | | | | | | | | | | | | | | This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change in commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Update T1042RDB.h in config folderPrabhakar Kushwaha2014-02-03-7/+8
| | | | | | | | | | | | | | Add usb2 node entry to hwconfig default Remove DDR controller interleaving from hwconfig Move SPI related macros out of "#ifdef CONFIG_SPIFLASH" Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Fix commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc: mpc85xx: move CONFIG_MPC85xx definition to CPU config.mkMasahiro Yamada2014-01-24-1/+0
| | | | | | | Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk because all target boards with mpc85xx cpu define it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/mpc85xx:Increase binary size for P, B & T series boards.Prabhakar Kushwaha2014-01-21-8/+8
| | | | | | | | | | | u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* kgdb: configs: remove obsolete CONFIG_KGDB_SER_INDEXVladimir Zapolskiy2013-12-13-1/+0
| | | | | | | | The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years ago in commits 550650ddd0 and bf16500f79, either kgdb subsystem should care about this parameter or it should be gone completely. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-1/+1
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: Add T1042RDB_PI board supportPriyanka Jain2013-11-13-0/+694
T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Two on-board RGMII 10/100/1G ethernet ports. - SERDES Connections, 8 lanes supporting: — PCI — SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Video - DIU supports video at up to 1280x1024x32bpp - HDMI connector - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
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