arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	powerpc/85xx: move SRIO configuration out of corenet_ds.h	Timur Tabi	2012-10-22	-0/+4
\| \| \| \| \| \| \| \|	The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	powerpc/fsl-corenet: remove dead variant symbols	Scott Wood	2012-08-23	-1/+1
\| \| \| \| \| \| \| \| \| \| \|	These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
*	powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h	Timur Tabi	2011-11-29	-1/+0
\| \| \| \| \| \| \| \| \| \| \|	Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA controller, so it should be defined in config_mpc85xx.h instead of the various board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013, P1022, P2041, P3041, P5010, and P5020. It was already defined for the P1010 and P1014. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Add support for RMan LIODN initialization	Kumar Gala	2011-10-18	-0/+1
\| \| \| \| \| \| \| \| \|	This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Add support for setting up RAID engine liodns on P5020	Kumar Gala	2011-10-03	-0/+1
\| \| \| \| \| \| \| \| \|	Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Refactor some defines out of corenet_ds.h	Kumar Gala	2011-10-03	-0/+5
\| \| \| \| \| \| \| \| \| \| \|	Move some SoC/board specific defines out of corenet_ds.h and into the corresponding P3041DS/P4080DS/P5020.h. We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060 SoC/reference board does not have these devices and it will share the same board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	Minor coding style cleanup.	Wolfgang Denk	2011-05-19	-1/+0
\| \| \| \|	Signed-off-by: Wolfgang Denk <wd@denx.de>
*	powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)	Kumar Gala	2011-04-27	-0/+37
	The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>