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* ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DSKumar Gala2009-09-24-0/+4
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-1/+0
| | | | | | | | | | | | | The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Removed BEDBUG support from FSL 85xx boardsKumar Gala2009-08-10-1/+0
| | | | | | | | | For some reason the MPC8544 enabled BEDBUG if PCI was enabled and that got copied int the MPC8536, MPC8572 and P2020 DS boards. The BEDBUG support has never been made to work completely on e500/85xx so we just disable it to save space and match the other FSL 85xx boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Report which "bank" of NOR flash we are booting from on FSL boardsKumar Gala2009-07-22-0/+5
| | | | | | | | | | | | | | The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of swizzling the upper address bits of the NOR flash we boot out of which creates the concept of "virtual" banks. This is useful in that we can flash a test of image of u-boot and reset to one of the virtual banks while still maintaining a working image in "bank 0". The PIXIS FPGA exposes registers on LBC which we can use to determine which "bank" we are booting out of (as well as setting which bank to boot out of). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Bump up the BOOTMAP to 16M on FSL 85xx boardsKumar Gala2009-07-21-2/+2
| | | | | | | | We have always mapped at least 16M in the kernel and we have seen cases with new kernel features that a kernel image needs more than 8M of memory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* remove _IO_BASE and KSEG1ADDR from board configuration filesTimur Tabi2009-07-11-6/+0
| | | | | | | | | | | | | | | | The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet driver, but the code that used that macro was removed over a year ago, so board configuration files no longer need to define it. The _IO_BASE macro is also automatically defined to 0 if it isn't already set, so there's no need to define that macro either in the board configuration files. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* 8xxx: Fix PCI bus address setup for 36-bit configsKumar Gala2009-06-30-3/+3
| | | | | | | | | | | We want the outbound PCI memory map to end at the 4G boundary so we can maximize the amount of space available for inbound mappings if we have large amounts of memory. This matches the device tree setup in the kernel for the 36-bit physical configs for the platforms that have one (MPC8641 HPCN & MPC8572 DS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* i2c: Remove deprecated individual i2c commandsPeter Tyser2009-06-12-1/+0
| | | | | | | | | | | | | The following individual I2C commands have been removed: imd, imm, inm, imw, icrc32, iprobe, iloop, isdram. The functionality of the individual commands is still available via the 'i2c' command. This change only has an impact on those boards which did not have CONFIG_I2C_CMD_TREE defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 85xx: Fix address map for 36-bit config of MPC8572DSKumar Gala2009-02-16-3/+6
| | | | | | | | | | When we introduced the 36-bit config of the MPC8572DS board we had the wrong PCI MEM bus address map. Additionally, the change to the address map exposes a small issue in our dummy read on the ULI bus. We need to use the new mapping functions to handle that read properly in the 36-bit config. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-0/+1
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add a 36-bit physical configuration for MPC8572DSKumar Gala2009-01-23-1/+46
| | | | | | | We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Handle eLBC difference w/36-bit physicalKumar Gala2009-01-23-0/+1
| | | | | | | | | | | | The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use BR_ADDR macro for NAND chipselectsKumar Gala2009-01-23-4/+4
| | | | | | | | | Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boardsKumar Gala2009-01-23-1/+4
| | | | | | | | | Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boardsKumar Gala2009-01-23-3/+6
| | | | | | | | | Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-5/+5
| | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-6/+6
| | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: separate FLASH BASE virtual from physical addressKumar Gala2009-01-23-4/+5
| | | | | | | | | | Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: separate PIXIS virtual from physical addressKumar Gala2009-01-23-1/+2
| | | | | | | | | | Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger2009-01-23-1/+0
| | | | | | | | | | | | | | | | This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Some changes of TLB entry setting for MPC8572DSHaiying Wang2009-01-13-0/+1
| | | | | | | | | | - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Remove unused CONFIG_ADDR_STREAMING definesPeter Tyser2008-12-14-1/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 85xx: fix the wrong DDR settings for MPC8572DSDave Liu2008-12-04-13/+13
| | | | | | | | The default DDR freq is 400MHz or 800M data rate, the old settings is pure wrong for the default case. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Removed unused CONFIG_L1_INIT_RAM symbol.Jon Loeliger2008-12-03-2/+0
| | | | | | | | Prevent further viral propogation of the unused symbol CONFIG_L1_INIT_RAM by just removing it. Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: remove the unused ddr_enable_ecc in the board fileDave Liu2008-12-03-0/+1
| | | | | | | | | | The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-11-02-32/+31
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* NAND: Fix CONFIG_ENV_ADDR for MPC8572DSHaiying Wang2008-10-31-1/+1
| | | | | | | CONFIG_ENV_ADDR should be (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE). Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NAND: Add support for MPC8572DS boardHaiying Wang2008-10-29-1/+55
| | | | | | | | | | | | | This patch defines 1M TLB&LAW size for NAND on MPC8572DS, assigns 0xffa00000 for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file. It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image, to make room for the increased code size with NAND enabled. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-5/+0
| | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* 85xx: Enable 64-bit PCI resources on all Freescale boardsKumar Gala2008-10-24-0/+1
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* 85xx: remove unused config definitionDave Liu2008-10-24-10/+0
| | | | Signed-off-by: Dave Liu <daveliu@freescale.com>
* Enabled the Freescale SGMII riser card on 8572DSLiu Yu2008-10-18-0/+24
| | | | | | | This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-1/+2
| | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xx: Enable interrupt and setexpr commands on Freescale 85xx boardsKumar Gala2008-10-18-0/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-129/+129
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* MPC8572DS: Fix compile warningsKumar Gala2008-10-08-1/+1
| | | | | | | | | | Commit 445a7b38308eb05b41de74165b20855db58c7ee5 introduced the following compile warnings: cmd_i2c.c:112: warning: missing braces around initializer cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]') Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add ID EEPROM support for MPC8572DSHaiying Wang2008-10-07-0/+11
| | | | | | | The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for system information like mac addresses etc. This patch enables it. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Minor fixes for I2C address on MPC8572DSHaiying Wang2008-10-07-2/+6
| | | | | | | MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1 according to the board spec, and adds the 2nd i2c bus offset. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-4/+4
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-0/+576
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-27 21:34:42 +0000