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path: root/include/configs/MPC8548CDS.h
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* 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-0/+1
| | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Get ride of old TLB setup codeKumar Gala2008-01-17-1/+0
| | | | | | | Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8541/MPC8555/MPC8548 CDS to new TLB setupKumar Gala2008-01-17-0/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert MPC8541/MPC8555/MPC8548 CDS over to use new LAW init codeKumar Gala2008-01-16-0/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-7/+0
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Handle MPC85xx PCIe reset errata (PCI-Ex 38)Kumar Gala2007-12-11-0/+1
| | | | | | | On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update Freescale MPC85xx ADS/CDS/MDS board configKumar Gala2007-12-11-0/+1
| | | | | | * Enabled CONFIG_CMD_ELF Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update Freescale MPC85xx ADS/CDS/MDS board configKumar Gala2007-12-11-88/+2
| | | | | | | * Removed some misc environment setup * Enabled CONFIG_CMDLINE_EDITING Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update MPC85xx CDS to use libfdtKumar Gala2007-12-11-8/+3
| | | | | | | Updated the MPC85xx CDS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Improve handling of PCI interrupt device tree fixup on MPC85xx CDSKumar Gala2007-10-19-0/+1
| | | | | | | | | | | | | | | On the MPC85xx CDS we have two issues: 1. The device tree fixup code did not check to see if the property we are trying to update is actually found. Its possible that it would update random memory starting at 0. 2. Newer Linux kernel's have moved the location of the PCI nodes to be sibilings of the soc node and not children. The explicit PATH to the PCI node would not be found for these device trees. Add the ability to handle both paths. In the future we shouldn't handle such fixups by explicit path. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8548cds fixesEd Swarthout2007-08-29-9/+6
| | | | | | | | | | Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the correct consoledev needed for linux boot. Standardize on fdt{file,addr} var to hold dtb file name. Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* fdt: remove unused OF_FLAT_TREE_MAX_SIZE referencesKim Phillips2007-08-29-3/+0
| | | | | | and make some minor corrections to the FDT part of the README. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add CONFIG_HAS_ETH0 to all boards with TSECAndy Fleming2007-08-16-0/+1
| | | | | | | | | The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether to update TSEC1's device-tree node, so we need to add it to all the boards with TSECs. Do this for 83xx and 86xx, too, since they will eventually do something similar. Signed-off-by: Andy Fleming <afleming@freescale.com>
* Define tsec flag values in config filesAndy Fleming2007-08-16-0/+4
| | | | | | | | | | The tsec_info structure and array has a "flags" field for each ethernet controller. This field is the only reason there are settings. Switch to defining TSECn_FLAGS for each controller in the config header, and we can greatly simplify the array, and also simplify the addition of future boards. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xxCDS: Add make targets for legacy systems.Randy Vinson2007-08-14-0/+8
| | | | | | | | The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson <rvinson@mvista.com>
* Fix minor 85xx warningsAndy Fleming2007-08-14-2/+4
| | | | | | | | | | | Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming <afleming@freescale.com>
* 8548cds PCIE support.Ed Swarthout2007-08-14-106/+231
| | | | | | | | | | | | | | | | | | | | Make the early L1 cache stack region guarded to prevent speculative fetches outside the locked range. Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. init.S whitespace cleanup. Allow TEXT_BASE value to be specified on command line. This allows it to be set to 0xfffc0000 which cuts the uboot binary in half. Clear and enable lbc and ecm errors. Update last_busno in device-tree for pci and pcie. Remove load of obsolete cpu/mpc85xx/pci.0 Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*.Jon Loeliger2007-07-10-0/+9
| | | | | | | | | Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* include/configs: Use new CONFIG_CMD_* in 85xx board config files.Jon Loeliger2007-07-05-14/+14
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECxKim Phillips2007-05-17-8/+8
| | | | | | | For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Cleaned up some 85xx PCI bugsAndy Fleming2007-05-02-4/+4
| | | | | | | | | | | * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix PCI I/O space mapping on Freescale MPC85x0ADSSergei Shtylyov2007-04-23-1/+1
| | | | | | | | | | | | | | | | | | | | The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's describing the local address window used for the PCI I/O space accesses -- fix this and carry over the necessary changes into the MPC8560ADS code since the PCI I/O space mapping was also broken for this board (by the earlier commit 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how the PCI I/O space must be mapped to all the MPC85xx board config. headers. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> board/mpc8540ads/init.S | 4 ++-- board/mpc8560ads/init.S | 4 ++-- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 6 files changed, 12 insertions(+), 13 deletions(-)
* u-boot: Disables MPC8548CDS 2T_TIMING for DDR by defaultebony.zhu@freescale.com2007-04-23-1/+1
| | | | | | This patch disables MPC8548CDS 2T_TIMING for DDR by default. Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
* u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS boardZang Roy-r619112007-04-23-8/+20
| | | | | | Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* Merge with /home/wd/git/u-boot/masterWolfgang Denk2006-10-24-7/+16
|\ | | | | | | | | (Conflicts between Jon Loeliger's and Matthew McClintock's tree were resolved by in favour of Jon's version.)
| * Converted all 85xx boards to use a common FSL I2C driver.Jon Loeliger2006-10-20-2/+6
| | | | | | | | | | | | | | | | Introduced COFIG_FSL_I2C to select the common FSL I2C driver. And removed hard i2c path from a few u-boot.lds scipts too. Minor whitespace cleanups along the way. Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * Updated config headers to add default FDT-based bootingAndy Fleming2006-09-19-5/+8
| |
| * Add support for eTSEC 3 & 4 on 8548 CDSAndy Fleming2006-09-19-1/+3
| | | | | | | | | | | | | | * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems
| * * Added VIA configuration tableMatthew McClintock2006-08-09-14/+9
| | | | | | | | | | | | | | * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
| * * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon ↵Matthew McClintock2006-08-09-0/+12
| | | | | | | | | | | | Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | * Added VIA configuration tableMatthew McClintock2006-06-28-14/+9
| | | | | | | | | | | | | | * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* | * Add Flat Dev Tree construction for MPC85xx ADS and CDS boardsMatthew McClintock2006-06-28-0/+12
|/ | | | | | Patch by Jon Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger <jdl@freescale.com>
* * Patch by Jon Loeliger, 2005-05-05Jon Loeliger2005-07-25-0/+521
Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
generated by cgit v1.1 at 2024-10-30 11:55:54 +0000