summaryrefslogtreecommitdiff
path: root/include/configs/MPC8544DS.h
Commit message (Collapse)AuthorAgeLines
* FSL DDR: Convert MPC8544DS to new DDR code.Kumar Gala2008-08-27-18/+20
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/mtd: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-1/+1
| | | | | | rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Clean up INIT_RAM optionsAndy Fleming2008-07-14-17/+5
| | | | | | | | | The L2_INIT_RAM option was unused, and recent changes to the TLB code meant that the INIT_RAM TLBs weren't being cleared out. In order to reduce the amount of mapped space attached to nothing, we change things so the TLBs get cleared. Signed-off-by: Andy Fleming <afleming@freescale.com>
* Remove fake flash bank from 8544 DSAndy Fleming2008-07-14-2/+2
| | | | | | | | The fake flash bank was generating errors for anyone who didn't have a PromJET hooked up to the board. As that constitutes the vast majority of users, we remove it. Signed-off-by: Andy Fleming <afleming@freescale.com>
* MPC8544DS: Add ATI Video card supportKumar Gala2008-07-14-2/+22
| | | | | | Add support for using a PCIe ATI Video card on PCIe2. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Remove LBC_CACHE_BASE from 8544 DSAndy Fleming2008-07-14-2/+0
| | | | | | | | | | The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: remove dummy board_early_init_fKumar Gala2008-06-11-2/+0
| | | | | | | A number of board ports have empty version of board_early_init_f for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8544DS: Update config.hKumar Gala2008-06-11-1/+1
| | | | | | | * Enable flash progress * remove CLEAR_LAW0 since we dont really use it Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove unused and unconfigured memory test code.Kumar Gala2008-06-11-2/+0
| | | | | | | Remove unused and unconfigured DDR test code from FSL 85xx boards. Besides, other common code exists. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8544DS: Removes the unknown flash message informationRoy Zang2008-04-26-0/+1
| | | | | | | | | | This patch removes the unknown flash message information: '## Unknown FLASH on Bank 1 - Size = 0xdeadbeef = -286261248 MB' This unknown flash message is caused by PromJet. Some of the board user is unhappy with this information. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-0/+1
| | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Get ride of old TLB setup codeKumar Gala2008-01-17-1/+0
| | | | | | | Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert MPC8544 DS to new TLB setupKumar Gala2008-01-17-0/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: convert MPC8544 DS over to use new LAW init codeKumar Gala2008-01-16-0/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-7/+0
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Handle MPC85xx PCIe reset errata (PCI-Ex 38)Kumar Gala2007-12-11-0/+1
| | | | | | | On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update Freescale MPC85xx ADS/CDS/MDS board configKumar Gala2007-12-11-0/+1
| | | | | | * Enabled CONFIG_CMD_ELF Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update MPC8544 DS configKumar Gala2007-12-11-95/+12
| | | | | | | | | * Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2 * Removed some misc environment setup * Moved to using fdtfile & fdtaddr as fdt env var names * Enabled CONFIG_CMDLINE_EDITING Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update MPC8544DS to use libfdtKumar Gala2007-12-11-7/+3
| | | | | | | Updated the MPC8544DS config to use libfdt and assume use of aliases for ethernet, pci, and serial for the various fixups that are done. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Unify pixis_reset altbank across board familiesJason Jin2007-11-17-0/+1
| | | | | | | | Basically, refactor the CFG_PIXIS_VBOOT_MASK values into the separate board config files. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Fix ULI RTC support on MPC8544 DSKumar Gala2007-09-04-0/+3
| | | | | | | | | | | The RTC on the M1575 ULI chipset requires a dummy read before we are able to talk to the RTC. We accomplish this by adding a second memory region to the PHB the ULI is on and read from it. The second region is added to maintain compatiabilty with Linux's view of the PCI memory map. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* support board vendor-common makefilesKim Phillips2007-08-29-0/+1
| | | | | | | | | | | | | | | | | | if a board/$(VENDOR)/common/Makefile exists, build it. also add the first such case, board/freescale/common/Makefile, to handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as dictated by board configuration. thusly get rid of alternate build dir errors such as: FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory by putting the common/ mkdir command in its proper place (the common Makefile). Common bits from existing individual board Makefiles have been removed. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* fdt: remove unused OF_FLAT_TREE_MAX_SIZE referencesKim Phillips2007-08-29-3/+0
| | | | | | and make some minor corrections to the FDT part of the README. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Update MPC8544 DS PCI memory mapKumar Gala2007-08-16-12/+9
| | | | | | | | | | | The PCIe bus that the ULI M1575 is connected to has no possible way of needing more than the fixed amount of IO & Memory space needed by the ULI. So make it use far less IO & memory space and have it use the shared LAW. This free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed by each bus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix up some fdt issues on 8544DSKumar Gala2007-08-16-0/+1
| | | | | | | | It looks like we had a merge issue that duplicated a bit of code in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get the MAC address properly set in the device tree on boot for TSEC1 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Define tsec flag values in config filesAndy Fleming2007-08-16-5/+3
| | | | | | | | | | The tsec_info structure and array has a "flags" field for each ethernet controller. This field is the only reason there are settings. Switch to defining TSECn_FLAGS for each controller in the config header, and we can greatly simplify the array, and also simplify the addition of future boards. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 8544ds PCIE supportEd Swarthout2007-08-14-56/+79
| | | | | | | | | | | | | | | | | | PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*.Jon Loeliger2007-07-10-0/+9
| | | | | | | | | Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* include/configs: Use new CONFIG_CMD_* in 85xx board config files.Jon Loeliger2007-07-05-16/+17
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECxKim Phillips2007-05-17-4/+4
| | | | | | | For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add MPC8544DS main configuration file.Jon Loeliger2007-04-23-0/+591
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
generated by cgit v1.1 at 2024-11-15 15:27:48 +0000