summaryrefslogtreecommitdiff
path: root/include/configs/MPC837XERDB.h
Commit message (Collapse)AuthorAgeLines
* mpc83xx: bump loadaddr over fdtaddr to 0x500000Kim Phillips2008-04-25-1/+1
| | | | | | | | this seems as a good compromise between human memory, typing, and last but not least, to accommodate for current and future kernel bloat. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Fix the SATA clock setting of 837x targetsDave Liu2008-04-11-1/+1
| | | | | | | | | | | | | | | Currently the SATA controller clock is configured as CSB clock, usually the CSB clock is 400/333/266MHz. However, The SATA IP block is only guaranteed to operate up to 200 MHz as stated in the HW spec. The bug is reported by Joe D'Abbraccio <ljd015@freescale.com> This patch makes the SATA clock as half of CSB clock. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: enable the SATA interface on mpc8315 rdb and mpc837x rdb boardsKim Phillips2008-03-28-0/+23
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx/fdt_support: let user specifiy FSL USB Dual-Role controller roleAnton Vorontsov2008-03-25-0/+2
| | | | | | | | | Linux understands "host" (default), "peripheral" and "otg" (broken). Though, U-Boot doesn't restrict dr_mode variable to these values (think of renames in future). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Set PCI I/O bus-address base to zero.Scott Wood2008-03-25-1/+1
| | | | | | | | | | The device trees for these boards describe PCI I/O as starting from address zero from the device's perspective. Placing I/O elsewhere may cause problems with certain PCI boards, and may cause problems with Linux. Signed-off-by: Scott Wood <scottwood@freescale.com>
* 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boardsAnton Vorontsov2008-03-25-0/+1
| | | | | | This is primarily for the early console support. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: initialize serdes for MPC837XRDB boardsAnton Vorontsov2008-03-25-0/+6
| | | | | | | | On the MPC8377ERDB: 2 SATA and 2 PCI-E. On the MPC8378ERDB: 2 PCI-E On the MPC8379ERDB: 4 SATA Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: nand support for MPC837XRDB boardsAnton Vorontsov2008-03-25-0/+19
| | | | Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
* 83xx: Add Vitesse VSC7385 firmware uploadingTimur Tabi2008-03-25-26/+57
| | | | | | | | | | Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. Cleaned up the board header files to make selecting the VSC7385 easier to control. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: make dtb basename file references equal those of linuxKim Phillips2008-03-07-1/+1
| | | | | | | the dts file basenames were updated in linux - this helps avoid inadvertently loading any old dtbs laying around. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Add support for the MPC837xERDBKim Phillips2008-01-16-0/+596
MPC837xERDB board support includes: * DDR2 330MHz hardcoded (soldered on the board) * Local Bus NOR Flash * I2C, UART and RTC * eTSEC RGMII (TSEC0 - RTL8211B with MII; * TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware * load) Signed-off-by: Kevin Lam <kevin.lam@freescale.com> Signed-off-by: Joe D'Abbraccio <joe.d'abbraccio@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
generated by cgit v1.1 at 2024-11-02 02:02:54 +0000