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* fsl_esdhc: Fix esdhc disabled problem on some platformsChenhui Zhao2011-01-14-0/+1
| | | | | | | | | | | | Some new platform's esdhc pins don't share with other function. The eSDHC shouldn't be disabled, even if "esdhc" isn't defined in hwconfig env variable. Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated valueWolfgang Denk2010-10-26-2/+1
| | | | | | | | | | | | | | | | | | CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZEWolfgang Denk2010-10-26-2/+2
| | | | | | | | | | | | | | | | | | CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be some end address; to make the meaning more clear we rename it into CONFIG_SYS_INIT_RAM_SIZE No other code changes are performed in this patch, only minor editing of white space (due to the changed length) and the comments was done, where noticed. Note that the code for the PATI and cmi_mpc5xx board configurations looks seriously broken. Last known maintainers on Cc: Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Denis Peter <d.peter@mpl.ch> Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc: Cleanup BOOTFLAG_* referencesPeter Tyser2010-10-18-8/+0
| | | | | | | | | | | | Now that warm booting is not supported, there isn't a need for the BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them. Note that this change makes the board info bd_bootflags field useless. It will always be set to 0, but we leave it around so that we don't break the board info structure that some OSes are expecting to be passed from U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Makefile: move all Power Architecture boards into boards.cfgWolfgang Denk2010-10-18-0/+2
| | | | | | | | | | Clean up Makefile, and drop a lot of the config.mk files on the way. We now also automatically pick all boards that are listed in boards.cfg (and with all configurations), so we can drop the redundant entries from MAKEALL to avoid building these twice. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Rename TEXT_BASE into CONFIG_SYS_TEXT_BASEWolfgang Denk2010-10-18-1/+1
| | | | | | | | | | | | The change is currently needed to be able to remove the board configuration scripting from the top level Makefile and replace it by a simple, table driven script. Moving this configuration setting into the "CONFIG_*" name space is also desirable because it is needed if we ever should move forward to a Kconfig driven configuration system. Signed-off-by: Wolfgang Denk <wd@denx.de>
* e300: increase CONFIG_SYS_BOOTMAPSZ to allow booting large kernelsIra W. Snyder2010-09-23-2/+2
| | | | | | | | | | | | | | Newer Linux kernels can overrun the initial memory window used for booting with their BSS area. When this happens, they overwrite the FDT and silently fail to boot. On e300 CPUs, the Linux kernel uses an initial BAT covering the first 256MB of RAM. See arch/powerpc/kernel/head_32.S for details. Increase the value of CONFIG_SYS_BOOTMAPSZ to accommodate the maximum value allowed by Linux. This will allow very large kernels to boot. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Remove unused CONFIG_SERIAL_SOFTWARE_FIFO featureStefan Roese2010-09-23-1/+0
| | | | | | | | | This patch removes the completely unused CONFIG_SERIAL_SOFTWARE_FIFO feature from U-Boot. It has only been implemented for PPC4xx and was not used at all. So let's remove it and make the code smaller and cleaner. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* powerpc: Update configs to properly set FSL_ELBCBecky Bruce2010-07-16-0/+1
| | | | | | | | | | | Some parts that have an Enhanced Local Bus Controller weren't setting CONFIG_FSL_ELBC. Fix this so we can use this define properly going forward (currently it's only used if PHYS_64BIT is set, which meant not all platforms needed to have it set correctly). Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: turn on icache in core initialization to improve u-boot boot timeKim Phillips2010-04-22-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | before, MPC8349ITX boots u-boot in 4.3sec: column1 is elapsed time since first message column2 is elapsed time since previous message column3 is the message 0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX 0.000 0.000: 0.000 0.000: Reset Status: 0.000 0.000: 0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.032 0.000: Board: Freescale MPC8349E-mITX 0.032 0.000: UPMA: Configured for compact flash 0.032 0.000: I2C: ready 0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 1.516 1.456: FLASH: 16 MB 2.641 1.125: PCI: Bus Dev VenId DevId Class Int 2.652 0.011: 00 10 1095 3114 0180 00 2.652 0.000: PCI: Bus Dev VenId DevId Class Int 2.652 0.000: In: serial 2.652 0.000: Out: serial 2.652 0.000: Err: serial 2.682 0.030: Board revision: 1.0 (PCF8475A) 3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic 3.080 0.000: TSEC0, TSEC1 4.300 1.219: IDE: Bus 0: .** Timeout ** after, MPC8349ITX boots u-boot in 3.0sec: 0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX 0.010 0.000: 0.010 0.000: Reset Status: 0.010 0.000: 0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.017 0.000: Board: Freescale MPC8349E-mITX 0.038 0.020: UPMA: Configured for compact flash 0.038 0.000: I2C: ready 0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 0.260 0.222: FLASH: 16 MB 1.390 1.130: PCI: Bus Dev VenId DevId Class Int 1.390 0.000: 00 10 1095 3114 0180 00 1.390 0.000: PCI: Bus Dev VenId DevId Class Int 1.400 0.010: In: serial 1.400 0.000: Out: serial 1.400 0.000: Err: serial 1.400 0.000: Board revision: 1.0 (PCF8475A) 1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic 1.832 0.000: TSEC0, TSEC1 3.038 1.205: IDE: Bus 0: .** Timeout ** also tested on these boards (albeit with a less accurate boottime measurement method): seconds: before after 8349MDS ~2.6 ~2.2 8360MDS ~2.8 ~2.6 8313RDB ~2.5 ~2.3 #nand boot 837xRDB ~3.1 ~2.3 also tested on an 8323ERDB. v2: also remove the delayed icache enablement assumption in arch ppc's board.c, and add a CONFIG_MPC83xx define in the ITX config file for consistency (even though it was already being defined in 83xx' config.mk). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: enable command line autocompletionKim Phillips2010-04-22-0/+1
| | | | | | because it's convenient. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: remove hardcoded network addresses from config filesKim Phillips2010-02-22-2/+0
| | | | | | | and avoid e.g., two identical boards from causing random networking conflicts when hooked up to the same network. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOULHeiko Schocher2009-12-08-3/+0
| | | | | | | | | There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher <hs@denx.de>
* mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfieldsKim Phillips2009-09-26-1/+2
| | | | | | | | | | | | | | | | | | | some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS_<registername>_<bitfield> assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: accommodate larger kernel sizes by defaultKim Phillips2009-08-21-2/+2
| | | | | | | linux mpc83xx_defconfig kernels are getting bigger, accommodate for their growth by adjusting default load and fdt addresses. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: CONFIG_83XX_GENERIC_PCI is now synonymous with CONFIG_PCI; remove ↵Kim Phillips2009-07-27-2/+1
| | | | | | the former Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: MPC837XEMDS: Fixup eSDHC nodes in device treeAnton Vorontsov2009-07-16-0/+1
| | | | | | | | | | | fdt_fixup_esdhc() will either disable or enable eSDHC nodes, and also will fixup clock-frequency property. Plus, since DR USB and eSDHC are mutually exclusive, we should only configure the eSDHC if asked through hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser2009-06-12-1/+1
| | | | | | | | Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xxPeter Tyser2009-06-12-1/+1
| | | | | | | | Use the standard lowercase "xx" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* rename CONFIG_CMD_ENV to CONFIG_CMD_SAVEENVMike Frysinger2009-02-18-1/+1
| | | | | | | | The CONFIG_CMD_ENV option controls enablement of the `saveenv` command rather than a generic "env" command, or anything else related to the environment. So, let's make sure the define is named accordingly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 83xx: Add eSDHC support on 8379 EMDS boardAndy Fleming2009-02-16-0/+15
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'next'Kim Phillips2009-01-23-0/+21
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| * mpc83xx: Add PCI-E support for MPC837XEMDS boardsAnton Vorontsov2009-01-21-0/+21
| | | | | | | | | | | | | | | | | | | | | | MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger2009-01-23-1/+0
|/ | | | | | | | | | | | | | | | This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mpc83xx: add support for switching between USB Host/Function for MPC837XEMDSAnton Vorontsov2008-10-21-0/+2
| | | | | | | | | | With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add ELBC NAND support for the MPC837XEMDS boardsAnton Vorontsov2008-10-21-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-21-0/+3
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add SGMII riser module support for the MPC8378E-MDS boardsAnton Vorontsov2008-10-21-0/+2
| | | | | | | | | | This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-172/+172
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc83xx: add h/w flash protection to board configsKim Phillips2008-09-24-0/+1
| | | | | | | | the operating system may leave flash in a h/w locked state after writing. This allows u-boot to continue to write flash by enabling h/w unlocking by default. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-6/+6
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_NOWHERE in CONFIG_ENV_IS_NOWHEREJean-Christophe PLAGNIOL-VILLARD2008-09-10-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* drivers/mtd: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-1/+1
| | | | | | rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* 83xx/85xx: further localbus cleanupsAnton Vorontsov2008-06-10-1/+1
| | | | | | | | | | | | | move the BRx_* and ORx_* left behind in mpc85xx.h The same is needed for mpc8xx.h and mpc8260.h (defines are almost the same, just few differences which needs some attention though). But the bad news for mpc8xx and mpc8260 is that there are a lot of users of these defines. So this cleanup I'll leave for the "better times". Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* PPC: Create and use CONFIG_HIGH_BATSBecky Bruce2008-06-03-0/+1
| | | | | | | | | | | Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc83xx: bump loadaddr over fdtaddr to 0x500000Kim Phillips2008-04-25-1/+1
| | | | | | | | this seems as a good compromise between human memory, typing, and last but not least, to accommodate for current and future kernel bloat. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Dave Liu <daveliu@freescale.com>
* mpc83xx: Fix the SATA clock setting of 837x targetsDave Liu2008-04-11-1/+1
| | | | | | | | | | | | | | | Currently the SATA controller clock is configured as CSB clock, usually the CSB clock is 400/333/266MHz. However, The SATA IP block is only guaranteed to operate up to 200 MHz as stated in the HW spec. The bug is reported by Joe D'Abbraccio <ljd015@freescale.com> This patch makes the SATA clock as half of CSB clock. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: enable the SATA interface on mpc837xemds boardDave Liu2008-03-28-0/+23
| | | | | | | | Enable the first two SATA interfaces on MPC837xEMDS board, The two SATA ports are on LYNX1. (SATA0/1 on J4/5) Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: initialize serdes for MPC837xEMDS boardsDave Liu2008-03-28-0/+5
| | | | | | | | | | | | | | | This patch is stolen from Anton Vorontsov's patch for mpc837xerdb boards. The reference clk and xcorevdd voltage of serdes1/2 is same between mpc837xemds and mpc837xerdb. 8377E: LYNX1- 2 SATA LYNX2- 2 PCIE 8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE 8379E: LYNX1- 2 SATA LYNX2- 2 SATA Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Set PCI I/O bus-address base to zero.Scott Wood2008-03-25-1/+1
| | | | | | | | | | The device trees for these boards describe PCI I/O as starting from address zero from the device's perspective. Placing I/O elsewhere may cause problems with certain PCI boards, and may cause problems with Linux. Signed-off-by: Scott Wood <scottwood@freescale.com>
* mpc83xx: make dtb basename file references equal those of linuxKim Phillips2008-03-07-1/+1
| | | | | | | the dts file basenames were updated in linux - this helps avoid inadvertently loading any old dtbs laying around. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 837xEMDS: Improve the system performanceDave Liu2008-03-07-1/+9
| | | | | | | | | 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode; 2. Raise the eTSEC emergency priority; 3. Use the highest IP blocks clock. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Remove #undef DEBUG from MPC83xx board header filesTimur Tabi2008-02-12-2/+0
| | | | | | | | | Remove the "#undef DEBUG" line from all Freescale 83xx board header files. The inclusion of this line makes it impossible to enable debug code in other source files, because "#define DEBUG" typically needs to be defined before any header files are included. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Make the code more readableDave Liu2008-01-10-6/+13
| | | | | | | Format the code, make it more readable Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Reduce the latency of DDRDave Liu2008-01-10-5/+5
| | | | | | | Reduce the AL from 2 to 1 clock to improve the performance. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Remove cache config from config.hDave Liu2008-01-10-9/+0
| | | | | | | clean up the cache config from configs.h of board Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: convert to using do_fixup_*()Kim Phillips2008-01-08-5/+1
| | | | | | | | | convert to using simpler mpc85xx style fdt update code; streamline by eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm the old school FLAT_TREE code from 83xx (since the sbc8349 was just converted over to using libfdt). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Remove CONFIG options related to OF that we dont use (on 837x)Kim Phillips2008-01-08-2/+0
| | | | | | continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions for 837xKim Phillips2008-01-08-1/+2
| | | | | | | | Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x. This change guarantees that the environment will be located on the first flash sector after the U-Boot image. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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