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path: root/include/configs/MPC8349EMDS.h
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* mpc83xx: Fix config of Arbiter, System Priority, and Clock ModeKumar Gala2007-03-02-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: add command line editing by defaultKim Phillips2007-03-02-0/+1
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* mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDSXie Xiaobo2007-03-02-8/+36
| | | | | | | MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
* mpc83xx: Update 83xx to use fsl_i2c.cTimur Tabi2006-11-03-0/+1
| | | | | | | | Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-7/+7
| | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
* mpc83xx: add OF_FLAT_TREE bits to 83xx boardsKim Phillips2006-11-03-5/+46
| | | | | | | | | | add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and STDOUT_PATH configuration bits to mpc8349emds, mpc8349itx, and mpc8360emds board code. redo environment to use bootm with the fdtaddr for booting ARCH=powerpc kernels by default, and provide default fdtaddr values.
* Multi-bus I2C implementation of MPC834xBen Warren2006-11-03-2/+4
| | | | | | | | | | | | | | | | | | | | | Hello, Attached is a patch implementing multiple I2C buses on the MPC834x CPU family and the MPC8349EMDS board in particular. This patch requires Patch 1 (Add support for multiple I2C buses). Testing was performed on a 533MHz board. /*** Note: This patch replaces ticket DNX#2006083042000027 ***/ Signed-off-by: Ben Warren <bwarren@qstreams.com> CHANGELOG: Implemented driver-level code to support two I2C buses on the MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds are 50kHz, 100kHz and 400kHz on each bus. regards, Ben
* Minor cleanup.Wolfgang Denk2006-05-10-1/+1
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* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:Kumar Gala2006-04-20-47/+47
| | | | | | | | | - Removed MPC8349ADS port - Added PCI support to MPC8349ADS - reworked memory map to allow mapping of all regions with BATs Patch by Kumar Gala 20 Apr 2006 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Some code cleanupWolfgang Denk2006-04-16-2/+2
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* Support for DDR with 32-data path. Addotional notes on injectingRafal Jaworowski2006-03-16-14/+33
| | | | multiple-bit errors.
* Add command for handling DDR ECC registers on MPC8349EE MDS board.Marian Balakowicz2006-03-16-0/+1
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* Add initial support for MPC8349E MDS board.Marian Balakowicz2006-03-14-0/+696
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