| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
modify the CAS timings. my understanding is that these
settings decrease various wait times in the DDR interface.
Because these wait times are in clock cycles, and the DDR
clock on the 8315 RDB runs slower than on some other 83xx
platforms, we can dial down these values without a problem,
thereby decreasing the latency of memory a little.
Signed-off-by: Howard Gregory <Greg.Howard@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
| |
|
|
| |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
|
|
|
|
| |
the operating system may leave flash in a h/w locked state after writing.
This allows u-boot to continue to write flash by enabling h/w unlocking
by default.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
| |
|
|
| |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
| |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
| |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Freescale ships MPC8315E-RDB boards either with TSEC1 and USB UTMI
support, or without TSEC1 but with USB ULPI PHY support in addition.
With this patch user can specify desired USB PHY.
Also, it seems that we can't distinguish the two boards in software, so
user have to set `mpc8315erdb' environment variable to either 'tsec1'
(TSEC1 enabled) or `ulpi' (board with ULPI PHY, TSEC1 disabled), so that
Linux will not probe for TSEC1.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
| |/
|
|
|
|
| |
rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
move the BRx_* and ORx_* left behind in mpc85xx.h
The same is needed for mpc8xx.h and mpc8260.h (defines are almost
the same, just few differences which needs some attention though).
But the bad news for mpc8xx and mpc8260 is that there are a lot of users
of these defines. So this cleanup I'll leave for the "better times".
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
| |
|
|
|
|
|
|
|
|
|
| |
Change all code that conditionally operates on high bat
registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS
instead of the myriad ways this is done now. Define the option
for every config for which high bats are supported (and
enabled by early boot, on parts where they're not always
enabled)
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
|
| |
|
|
|
|
|
|
| |
this seems as a good compromise between human memory, typing,
and last but not least, to accommodate for current and future kernel bloat.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Dave Liu <daveliu@freescale.com>
|
| |
|
|
| |
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
| |
|
|
|
|
|
|
|
|
| |
The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.
Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| |
|
|
| |
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
|
|
The features list:
- Boot from NOR Flash
- DDR2 266MHz hardcoded configuration
- Local bus NOR Flash R/W operation
- I2C, UART, MII and RTC
- eTSEC0/1 support
- PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
