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* | | | | | mpc83xx: Add support for the MPC832XEMDS boardDave Liu2007-03-02-11/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | | | | | mpc83xx: streamline the 83xx immr head fileDave Liu2007-03-02-1680/+212
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
* | | | | [PATCH v3] Add sync to ensure flash_write_cmd is fully finishedHaiying Wang2007-02-21-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command is fully finished. The sync() is defined in each CPU's io.h file. For those CPUs which do not need sync for now, a dummy sync() is defined in their io.h as well. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* | | | | [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-42/+166
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] Update 440EPx/440GRx cpu detectionStefan Roese2007-01-31-2/+2
| |_|/ |/| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] Update 440SP(e) cpu revisionsStefan Roese2007-01-13-5/+8
| |/ |/| | | | | | | | | Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | Code cleanup.Wolfgang Denk2006-11-30-315/+315
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* | Merge with http://opensource.freescale.com/pub/scm/u-boot-83xx.gitWolfgang Denk2006-11-30-727/+2078
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| * | Make fsl-i2c not conflict with SOFT I2CJoakim Tjernlund2006-11-29-4/+0
| | | | | | | | | | | | Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: Update 83xx to use fsl_i2c.cTimur Tabi2006-11-03-102/+2
| | | | | | | | | | | | | | | | | | | | | | | | Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-4/+4
| | | | | | | | | | | | | | | | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and ↵Timur Tabi2006-11-03-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8360EMDS This patch also adds an improved I2C set_speed(), which handles all clock frequencies. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: add QE ethernet supportDave Liu2006-11-03-0/+2
| | | | | | | | | | | | this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
| * | mpc83xx: Add MPC8360EMDS basic board supportDave Liu2006-11-03-2/+14
| | | | | | | | | | | | | | | Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.
| * | mpc83xx: add the QUICC Engine (QE) immap fileDave Liu2006-11-03-0/+550
| | | | | | | | | | | | common QE immap file. Also required for 8360.
| * | mpc83xx: Add 8360 specifics to 83xx immapDave Liu2006-11-03-571/+1404
| | | | | | | | | | | | | | | Mainly add QE device dependencies, with appropriate 8360 protection. Lindent also run.
| * | mpc83xx: Add support for the MPC8349E-mITXTimur Tabi2006-11-03-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | Multi-bus I2C implementation of MPC834xBen Warren2006-11-03-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hello, Attached is a patch implementing multiple I2C buses on the MPC834x CPU family and the MPC8349EMDS board in particular. This patch requires Patch 1 (Add support for multiple I2C buses). Testing was performed on a 533MHz board. /*** Note: This patch replaces ticket DNX#2006083042000027 ***/ Signed-off-by: Ben Warren <bwarren@qstreams.com> CHANGELOG: Implemented driver-level code to support two I2C buses on the MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds are 50kHz, 100kHz and 400kHz on each bus. regards, Ben
| * | mpc83xx: Changed to unified mpx83xx names and added common 83xx changesDave Liu2006-11-03-93/+138
| |/ | | | | | | | | | | | | Incorporated the common unified variable names and the changes in preparation for releasing mpc8360 patches. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | [PATCH] PPC4xx: 440SP Rev. C detection addedStefan Roese2006-11-28-0/+1
|/ | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Use generic I2C register block on 85xx and 86xx.Jon Loeliger2006-10-20-76/+9
| | | | | | | Replace private IMMAP I2C structures with generic reg block and allow 86xx to have multiple I2C device busses. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.cJon Loeliger2006-10-19-0/+90
| | | | | | | in an effort to begin to unify the umpteen FSL I2C drivers that are all otherwise very similar. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Fixed leading whitespace issues.Jon Loeliger2006-10-13-3/+2
| | | | | | Removed spurious LAWAR thing. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Fix whitespace issues.Jon Loeliger2006-10-10-233/+233
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* Merge branch 'master' of http://www.denx.de/git/u-bootJon Loeliger2006-09-19-1/+6
|\ | | | | | | | | | | Conflicts: board/stxxtc/Makefile
| * Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese2006-09-07-1/+6
| | | | | | | | | | | | | | | | | | | | | | - Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
* | Merge branch 'mpc86xx'Jon Loeliger2006-09-14-2/+3
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| * | Handle 86xx SVR values according to the new Reference Manual.Jon Loeliger2006-09-14-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Both 8641 and 8641D have SVR == 0x8090, and are distinguished by the byte in bits 16-23 instead. Thanks to Jason Jin for noticing. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | Merge branch 'mpc86xx'Jon Loeliger2006-08-22-5/+5
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| * | Cleanup more poorly introduced whitespace.Jon Loeliger2006-08-22-5/+5
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* | | Merge branch 'mpc86xx'Jon Loeliger2006-08-22-9/+9
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| * | Cleanup poorly introduced whitespace.Jon Loeliger2006-08-22-9/+9
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* | | Merge branch 'mpc85xx'Jon Loeliger2006-08-09-2/+23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: include/ft_build.h include/pci.h Resolved, though.
| * | | * Added support for initializing second PCI bus on 85xx Patch by Andy ↵Matthew McClintock2006-08-09-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | | Merge branch 'wd'Jon Loeliger2006-08-09-0/+43
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| * | | Cleanup config file and bootup output for Yucca board.Marian Balakowicz2006-07-03-1/+1
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| * | | Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz2006-06-30-0/+43
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| | * | Add support for AMCC 440SPe CPU based eval board (Yucca).Marian Balakowicz2006-06-30-0/+43
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* | | | Merge branch 'mpc86xx'Jon Loeliger2006-06-27-30/+32
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| * | | Enable PCIE1 for MPC8641HPCN boardJin Zhengxiong-R641882006-06-27-30/+32
| | | | | | | | | | | | | | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* | | | Merge branch 'mpc86xx'Jon Loeliger2006-06-07-2/+2
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| * | | Update 86xx address map and LAWBARs.Jon Loeliger2006-05-19-2/+2
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* | | | Merge branch 'master' of http://www.denx.de/git/u-bootJon Loeliger2006-06-07-0/+2
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| * | | Add support for AMCC 440EP Rev C and 440GR Rev BStefan Roese2006-05-10-0/+2
| | | | | | | | | | | | | | | | Patch by John Otken, 08 May 2006
* | | | Merge branch 'mpc86xx'Jon Loeliger2006-05-09-4/+1393
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| * | Initial support for MPC8641 HPCN board.Jon Loeliger2006-04-26-4/+1393
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* | | Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:Kumar Gala2006-04-20-1/+1
|/ / | | | | | | | | | | | | | | | | - Removed MPC8349ADS port - Added PCI support to MPC8349ADS - reworked memory map to allow mapping of all regions with BATs Patch by Kumar Gala 20 Apr 2006 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Fix DDR ECC bit definitions for MPC83xx.Marian Balakowicz2006-03-16-2/+2
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* | Add DMA support for MPC83xx.Marian Balakowicz2006-03-14-1/+86
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* | Add bit definitions for MPC83xx DDR controller registers.Marian Balakowicz2006-03-14-0/+52
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generated by cgit v1.1 at 2024-11-14 21:51:38 +0000