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* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-08-02-0/+6
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| * Fix breakage of 8xx boards from recent commit.Rafal Jaworowski2007-07-19-0/+6
| | | | | | | | | | | | | | This patch fixes the negative consequences for 8xx of the recent "ppc4xx: Clean up 440 exceptions handling" commit. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* | ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese2007-07-16-0/+3
|/ | | | | | | | | | The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
* Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-23/+23
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* Merge with /home/stefan/git/u-boot/denx-440-exceptionsStefan Roese2007-06-15-1/+14
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| * ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc4xx] Extend 44x GPIO setup with default output stateStefan Roese2007-06-15-3/+5
|/ | | | | | | The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup is extended with the default GPIO output state (level). Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-34/+55
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| * ppc4xx: Update in_be32() functions and friends to latest Linux versionStefan Roese2007-06-01-34/+55
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-05-16-21/+57
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| * | mpc83xx: Add 831x support to global_data.hScott Wood2007-04-23-2/+4
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().Scott Wood2007-04-23-13/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than misleadingly define PVR_83xx as the specific type of 83xx being built for, the PVR of each core revision is defined. checkcpu() now prints the core that it detects, rather than aborting if it doesn't find what it thinks it wants. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mpc83xx: Add register definitions for MPC831x.Scott Wood2007-04-23-6/+50
| | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
* | | [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot messageGrzegorz Wianecki2007-05-05-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | | Add support for the 8568 MDS boardAndy Fleming2007-05-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | Enable 8544 supportAndy Fleming2007-04-23-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Add support to the Makefile * Add 8544 configuration support to the tsec driver * Add 8544 SVR numbers to processor.h Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nGAndy Fleming2007-04-23-2/+2
| | | | | | | | | | | | | | | | | | | | | The other pagesz constants use one letter to specify order of magnitude. Also change the one reference to it in mpc8548cds/init.S Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS boardZang Roy-r619112007-04-23-0/+1
|/ / | | | | | | | | | | Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xxWolfgang Denk2007-04-18-0/+3
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| * Merge branch 'master' into hpc2roy zang2007-02-28-44/+175
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/Makefile Fix the merge conflict in file drivers/Makefile Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * \ Merge branch 'master' into hpc2roy zang2007-02-12-2/+2
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| * \ \ Merge branch 'master' into hpc2roy zang2007-01-22-5/+8
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/cfi_flash.c The patch by Heiko Schocher <hs@pollux.denx.de> on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board.
| * \ \ \ Fix the confilcts when merging 'master' into hpc2.roy zang2006-12-01-798/+2150
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The conflicts due to a new mpc7448 p3m7448 board is in the main tree. Merge branch 'master' into hpc2 Conflicts: MAKEALL cpu/74xx_7xx/cpu.c cpu/74xx_7xx/cpu_init.c cpu/74xx_7xx/speed.c
| * | | | | General code modification for mpc7448hpc2 board support.roy zang2006-11-02-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add 7447A and 7448 processor support. 2. Add the following flags. CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically (such as by switch on board), this flag should be set. CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot relocates to RAM, this flag should be set. CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the system hang in exception, this flag should be set. There is a design issue for tsi108/109 pci configure read. When pci scan the slots, if there is no pci card, the tsi108/9 will cause a machine check exception for mpc7448 processor. Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* | | | | | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-03-31-0/+2
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| * \ \ \ \ \ Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xxWolfgang Denk2007-03-29-0/+2
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| | * | | | | | Set Rev 2.x 86xx PIC in mixed mode.Haiying Wang2007-03-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang <haiying.wang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | | | | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-0/+56
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| * | | | | | | [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-1/+12
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| * | | | | | [PATCH] Add AMCC PPC405EZ supportStefan Roese2007-03-21-1/+12
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X insteadKumar Gala2007-03-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | | | | mpc83xx: Add support for the MPC832XEMDS boardDave Liu2007-03-02-11/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | | | | | mpc83xx: streamline the 83xx immr head fileDave Liu2007-03-02-1680/+212
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
* | | | | [PATCH v3] Add sync to ensure flash_write_cmd is fully finishedHaiying Wang2007-02-21-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command is fully finished. The sync() is defined in each CPU's io.h file. For those CPUs which do not need sync for now, a dummy sync() is defined in their io.h as well. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* | | | | [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-42/+166
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] Update 440EPx/440GRx cpu detectionStefan Roese2007-01-31-2/+2
| |_|/ |/| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] Update 440SP(e) cpu revisionsStefan Roese2007-01-13-5/+8
| |/ |/| | | | | | | | | Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | Code cleanup.Wolfgang Denk2006-11-30-315/+315
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* | Merge with http://opensource.freescale.com/pub/scm/u-boot-83xx.gitWolfgang Denk2006-11-30-727/+2078
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| * | Make fsl-i2c not conflict with SOFT I2CJoakim Tjernlund2006-11-29-4/+0
| | | | | | | | | | | | Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: Update 83xx to use fsl_i2c.cTimur Tabi2006-11-03-102/+2
| | | | | | | | | | | | | | | | | | | | | | | | Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: Replace CFG_IMMRBAR with CFG_IMMRTimur Tabi2006-11-03-4/+4
| | | | | | | | | | | | | | | | | | | | | Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx tree matches the other 8xxx trees. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and ↵Timur Tabi2006-11-03-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8360EMDS This patch also adds an improved I2C set_speed(), which handles all clock frequencies. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | mpc83xx: add QE ethernet supportDave Liu2006-11-03-0/+2
| | | | | | | | | | | | this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
| * | mpc83xx: Add MPC8360EMDS basic board supportDave Liu2006-11-03-2/+14
| | | | | | | | | | | | | | | Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.
| * | mpc83xx: add the QUICC Engine (QE) immap fileDave Liu2006-11-03-0/+550
| | | | | | | | | | | | common QE immap file. Also required for 8360.
| * | mpc83xx: Add 8360 specifics to 83xx immapDave Liu2006-11-03-571/+1404
| | | | | | | | | | | | | | | Mainly add QE device dependencies, with appropriate 8360 protection. Lindent also run.
| * | mpc83xx: Add support for the MPC8349E-mITXTimur Tabi2006-11-03-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | Multi-bus I2C implementation of MPC834xBen Warren2006-11-03-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hello, Attached is a patch implementing multiple I2C buses on the MPC834x CPU family and the MPC8349EMDS board in particular. This patch requires Patch 1 (Add support for multiple I2C buses). Testing was performed on a 533MHz board. /*** Note: This patch replaces ticket DNX#2006083042000027 ***/ Signed-off-by: Ben Warren <bwarren@qstreams.com> CHANGELOG: Implemented driver-level code to support two I2C buses on the MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds are 50kHz, 100kHz and 400kHz on each bus. regards, Ben
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